• Perform failure analysis, define root causes of cycling failures, and drive for improvements in the test flow

• Interface with design, process, test and reliability engineering to solve problems.

• Define stress screens to deliver OEM grade product quality and meeting DPPM targets and validate the same

• Co-ordinate with Shanghai team to discuss and deliver improved screen tests to meet the optimum level of memory health.

• Analyze and program CELP(Code Excited Linear Prediction) principle which overcomes the hurdles in accurately reconstructing the residual signal information at lower bit rates.

• My work consisted of the design and implementation of CELP Codec(Coder-Decoder).

• The LPC (Linear Predictive Coding) technique consisted of LP analysis of speech where in I had to extract and rectify the LP parameters and coefficients

• Build a scheme to search the Predictive codebook and compute the excitation signal

• This implementation was executed using Vivado HLS by generating , synthesizable set of codes(High Level Synthesis Language) and generating the report including timing, Latency and hardware utilization.

• Other than generating optimal coding, one of my main challenges included exploring ways to regulate ,remodel the synthesizable codes the resulted in maximum optimization

• As a part of this project had to work on the interfaces and understand various segmented aspects of the PSoc 5LP developer Kit which ranged from functioning, architecture and software to develop applications.

• The segmented work consisting of both hardware and coding using the dev kit included LCD Display, running a DC Motor, Counter, OpAmp, ADC etc.

• Serial Line Implementation for windows Kernel using UART protocols of the dev kit with a PC which consisted of both hardware and software interfaces and coding