# Aishwarya Bhat > Intel Acceleration Office End-to-End Technical Program Manager & Director at Intel Corporation Location: Santa Clara, California, United States Profile: https://flows.cv/aishwaryabhat Passionate validation engineer with an extensive breadth of knowledge in handling complex product development programs from conception to launch. Leads and manages diverse global teams and mentors them to find their career best. Disciplined and organized individual with a knack for designing automated tools. Brings “calm to the chaos” and sought to put out fires. The go to person when it comes to designing innovative, agile and efficient solutions. A change agent who adds energy and creativity to the teams she interfaces with. Active community leader and volunteer with experience in development and delivery of educational programs. Specialties: Innovator, Change Agent, Strategist, Visionary, Leader, Getting Job Done, Deliver Results. ## Work Experience ### Intel Acceleration Office End-to-End Technical Program Manager & Director @ Intel Corporation Jan 2024 – Present Managing Intel's End-to-End Transformation Journey towards enabling IDM2.0 model for Intel Foundry, Manufacturing and Technology Development Organizations. ### Director of Quality Management Systems & Foundry Manufacturing Standards @ Intel Corporation Jan 2022 – Jan 2024 Led Intel Foundry Services (IFS) organization towards establishing their Quality Management Systems partnering closely with key business stakeholders internal and external to IFS including Legal, Finance, Engineering, Operations, Corporate Quality Network, Business Development. Steered the entire organization and its partners towards ISO/IATF Certification. Established the Foundry Manufacturing Standards for IFS and led the worldwide cross-organization team to deliver all manufacturing and operation solutions for IFS's inaugural customer. ### Director of Peoples Systems and Quality Systems @ Intel Corporation Jan 2021 – Jan 2022 Responsible for standing up the People Systems and Quality Systems for Intel Foundry Services (IFS) partnering closely with key business stakeholders internal and external to IFS including Human Resources, Legal, Finance, Engineering, Operations, Corporate Quality Network, Business Development and others. ### Technical Advisor to Corporate VP and GM of Product Enablement Solutions Group at Intel @ Intel Corporation Jan 2019 – Jan 2021 | Sac Partner with General Manager, his staff and peers across the corporation to drive key engineering initiatives and decision making. Work closely with GM to create and drive a productive, communicative and collaborative environment that is aligned to Org and Corporate business strategy ### Senior Technical Program Manager @ Intel Corporation Jan 2016 – Jan 2019 | Sacramento, California Area Senior Technical Program Manager managing Soft Intellectual Property portfolio and road map, organization plan and budget, and driving efficiency and agility across the division through data analytics. Manage Soft IP (Intellectual Property - synthesizable RTL), Software and Firmware delivery to >50 SoCs (~80% of SOCs across Intel) for Server/uServer, Data Center and Client Segments for 50+ IPs. Drive development of IP readiness/health indicators used by entire organization and it's SOC partners; Drive continuous improvement, efficiency and agility within organization using Statistical Analysis by data mining bugs, new feature requests post commits, daily regression data over past years Drive generational IP feature set development/closure and high quality drop commitments (RTL, SW/FW, validation, and architecture) to SOCs. Focal point for escalations from SOCs to IP Management. Chair critical IP forums which facilitate the 2 way exchange of SOC activity and IP development activity providing visibility for development issues, performance against schedule, and defect management across all SOCs and IP Developments and bringing front the core hot issues and gaps to executive management for timely closure. Provide weekly updates to GM/VP on execution status and escalations. ### Product Owner @ Intel Corporation Jan 2013 – Jan 2016 | San Francisco Bay Area Lead cross-functional Product Development Teams to deliver products for Intel Custom Foundry. Cross-functional methodologies and infrastructure enabling lead to drive nimble quality and efficient execution across teams. ### Software Manager @ Intel Corporation Jan 2010 – Jan 2013 Led a team of highly talented and diverse engineers to deliver high quality graphic drivers. Championed several new, unique, and agile software validation methods that delivered new features to market faster. Mentor and Coach to the team that unlocked their potential and drove high output from the team. ### Software Validation Architect and Test Planning Manager @ Intel Corporation Jan 2008 – Jan 2010 Responsible for defining, architecting, and implementing validation requirements and methods for graphics drivers. Identifing, defining and prototyping validation automation methods, test suite expectations, and test flows. Mentor and Drive the team to maximize test coverage while minimizing TPT and cost. ### Product Validation and Ramp Manager @ Intel Corporation Jan 2007 – Jan 2008 As a Product Validation Manager, I was responsible for overseeing post silicon product validation and defining/implementing synergistic methodologies across the division for all NAND Products. As a High Volume Manufacturing Manager ensuring fastest, smoothest and most economical high volume ramp for NAND Products. ### Product Development Team Lead @ Intel Corporation Jan 2006 – Jan 2007 Responsible for completing the product life cycle (PLC) phases from Design Implementation to High Volume Manufacturing Ramp for Intel's NAND Products. ### Technical Integrator and Product Validation Team Lead @ Intel Corporation Jan 2004 – Jan 2006 | Folsom, California Lead a globally dispersed and diverse team to define, develop and integrate new validation vectors for Flash Memory Products for both silicon wafers and packaged parts with a goal to optimize TTI and increase revenue through high yields and high quality. Defining and Implementing new validation vectors to validate Flash Memory Products for both silicon wafers and packaged parts, performing failure analysis to increase yield and quality ### Senior Product Development Engineer @ Intel Corporation Jan 1997 – Jan 2004 | Folsom, CA Defining and Implementing new validation vectors to validate Flash Memory Products for both silicon wafers and packaged parts, performing failure analysis to increase yield and quality ### SWE Mission Awards Coordinator & Awards Implementation Team Member @ Society of Women Engineers Jan 2023 – Present ### Program Director @ WITI (Women in Technology International) Jan 2013 – Present Developing impactful programs for WITI Sacramento Members. Growing the chapter's influence and awareness through strategic partnership with coporations. Volunteering my time to make a positive impact on the community while meeting some great and fun people. ## Education ### MS in Electrical and Electronics Engineering California State University-Sacramento ### Bachelors in Electrical and Electronics Engineering Bangalore University ## Contact & Social - LinkedIn: https://linkedin.com/in/abhat - Portfolio: http://www.intel.com - Portfolio: http://www.swe-goldenwest.org/sfs/ - Portfolio: http://www.folsomtrailsgs.webs.com --- Source: https://flows.cv/aishwaryabhat JSON Resume: https://flows.cv/aishwaryabhat/resume.json Last updated: 2026-04-10