RTL Power Estimation & Architecture Exploration | End-to-End Flow Leadership

Led the development and global deployment of Physical Aware RTL Power Estimation and Architecture Exploration solutions, driving innovation from specification to customer integration across leading technology nodes (3nm/5nm/7nm/14nm) at different foundries.

• Defined product specs from market and competitive analysis, owning the full technical roadmap across architecture, design, and validation.

• Delivered scalable, accurate RTL power prediction tools, deployed with customers Worldwide.

• Spearheaded Catapult-based library characterization and integrated internal P&R and synthesis tools for early area/delay estimation.

• Enabled third-party logic synthesis collaboration for early power/area prediction, improving design feasibility.

• Built a robust methodology and environment to guide RTL designers using the Catapult–Calibre flow for faster, data-driven architectural decisions.

• Led ARM hardening projects for Cortex‑A53, A55, and A72 across multiple technology nodes, including Samsung 14nm and TSMC 28nm, 16nm, and 7nm.

• Successfully delivered full RTL‑to‑GDSII methodology for Cortex‑A53 on Samsung 14nm, enabling customer adoption and integration into production flows.

• Conducted competitive benchmarking against industry alternatives, ensuring performance, scalability, and differentiation of ARM solutions.

• Drove physical verification and sign‑off using Mentor Graphics solutions such as Oasys SoC, Tessent, Nitro, and Calibre, ensuring accuracy and compliance across customer designs.

• Partnered with cross‑functional teams and customers to optimize flows, reduce design cycle times, and improve overall IC performance.

• Built a high-performing Product Engineering team from the ground up using local talent, focused on RTL-to-GDSII methodology—including Optimization, Floorplanning, Clock Tree Synthesis (CTS), and Logic-Level Floorplanning engines.

• Managed multiple customer engagements and led teams to drive RTL2GDS flows within IC Implementation product lines.

• Specialized in Logical/Physical RTL Synthesis, RTL Floorplanning, and P&R solutions, enhancing design efficiency.

• Collaborated with diverse customers across various design styles and application domains, adapting to different complexities and process geometries.

• Trained and mentored new Application Engineers, building internal expertise and strengthening customer support capabilities.

• Successfully deployed Olympus (Place & Route) solutions for Netlist‑to‑GDSII flows across multiple business units, including Automotive, Set‑Top Box, Central R&D (Library Group for test chips), and Wireless.

• Managed multi‑site responsibilities across Noida and Bangalore, ensuring consistent methodology adoption and customer success.

• Partnered with diverse engineering teams to integrate advanced design automation tools into production workflows, improving efficiency and accelerating time‑to‑market.

• Built strong customer relationships by tailoring solutions to specific design challenges and delivering hands‑on deployment support.

• Founding Application Engineer for Olympus (P&R), instrumental in launching the new Noida office from the ground up.

• Deployed Netlist‑to‑GDSII flows for customer design teams, ensuring smooth adoption of Olympus tools and methodologies.

• Took on start‑up style responsibilities, from infrastructure setup to customer engagement, gaining hands‑on experience in building operations from scratch.

• Collaborated with cross‑functional teams (R&D and Marketing)to establish best practices and deliver early success stories that positioned the office for long‑term growth.