# Ajay Mishra > Engineering Director Solutions Group, at Siemens EDA Location: Fremont, California, United States Profile: https://flows.cv/ajaymishra As Group Head of the Solutions Team, I lead the development and delivery of high-value solutions that address the architectural complexity of advanced SoCs—including High-Performance Computing, Neural Networks, and Automotive segments. I manage global campaigns for C-to-GDSII products and oversee diverse, cross-functional teams to meet strategic business goals. 👥 Management & Leadership I’ve built and led global teams across Morocco, Egypt, India, US, and Korea—aligning engineering execution with business strategy. My leadership includes budget planning, resource allocation, and mentoring high-performing teams to deliver on aggressive timelines. I’m passionate about simplifying technology complexity and enabling scalable innovation through structured product lifecycle management. 🤝 Customer Engagement One of my unique strengths is customer deployment—translating complex design methodologies into real-world success. I’ve led pre- and post-sales activities, supported global rollouts, and partnered with customers to optimize their PD flows and overcome domain boundary challenges. My solutions consistently improve IC performance and time-to-market. 🔄 Inter-Team Communication I collaborate closely with internal engineering, program management, and external partners to ensure PD implementation meets performance, power, and reliability goals. I’ve overseen final sign-offs for tape-out and proactively escalated risks and resource gaps. My communication style bridges technical depth with business clarity—driving alignment across functions and geographies. 🔧 Technical Expertise With 25+ years of experience across semiconductor design and EDA, I specialize in High-Level Synthesis, Logic Synthesis, STA, Place & Route, and Power Analysis. My technical foundation spans leading design houses (STMicroelectronics, Intel, Philips) and EDA innovators (Sierra DA, Mentor Graphics, Siemens EDA) across India, France, and the USA. I’ve driven architecture exploration, RTL-to-GDSII implementation, and performance optimization across complex SoC platforms. ## Work Experience ### Engineering Director Solutions Group @ Siemens EDA (Siemens Digital Industries Software) Jan 2017 – Present | Fremont, California, United States RTL Power Estimation & Architecture Exploration | End-to-End Flow Leadership Led the development and global deployment of Physical Aware RTL Power Estimation and Architecture Exploration solutions, driving innovation from specification to customer integration across leading technology nodes (3nm/5nm/7nm/14nm) at different foundries. • Defined product specs from market and competitive analysis, owning the full technical roadmap across architecture, design, and validation. • Delivered scalable, accurate RTL power prediction tools, deployed with customers Worldwide. • Spearheaded Catapult-based library characterization and integrated internal P&R and synthesis tools for early area/delay estimation. • Enabled third-party logic synthesis collaboration for early power/area prediction, improving design feasibility. • Built a robust methodology and environment to guide RTL designers using the Catapult–Calibre flow for faster, data-driven architectural decisions. ### Senior Product Deployment Manager @ Mentor Graphics Jan 2016 – Jan 2017 | Fremont, California, United States • Led ARM hardening projects for Cortex‑A53, A55, and A72 across multiple technology nodes, including Samsung 14nm and TSMC 28nm, 16nm, and 7nm. • Successfully delivered full RTL‑to‑GDSII methodology for Cortex‑A53 on Samsung 14nm, enabling customer adoption and integration into production flows. • Conducted competitive benchmarking against industry alternatives, ensuring performance, scalability, and differentiation of ARM solutions. • Drove physical verification and sign‑off using Mentor Graphics solutions such as Oasys SoC, Tessent, Nitro, and Calibre, ensuring accuracy and compliance across customer designs. • Partnered with cross‑functional teams and customers to optimize flows, reduce design cycle times, and improve overall IC performance. ### Senior Product Engineering Manager @ Mentor Graphics Jan 2012 – Jan 2016 | Noida Area, India • Built a high-performing Product Engineering team from the ground up using local talent, focused on RTL-to-GDSII methodology—including Optimization, Floorplanning, Clock Tree Synthesis (CTS), and Logic-Level Floorplanning engines. • Managed multiple customer engagements and led teams to drive RTL2GDS flows within IC Implementation product lines. • Specialized in Logical/Physical RTL Synthesis, RTL Floorplanning, and P&R solutions, enhancing design efficiency. • Collaborated with diverse customers across various design styles and application domains, adapting to different complexities and process geometries. ### Team Lead Place and Route @ Mentor Graphics Jan 2007 – Jan 2012 • Trained and mentored new Application Engineers, building internal expertise and strengthening customer support capabilities. • Successfully deployed Olympus (Place & Route) solutions for Netlist‑to‑GDSII flows across multiple business units, including Automotive, Set‑Top Box, Central R&D (Library Group for test chips), and Wireless. • Managed multi‑site responsibilities across Noida and Bangalore, ensuring consistent methodology adoption and customer success. • Partnered with diverse engineering teams to integrate advanced design automation tools into production workflows, improving efficiency and accelerating time‑to‑market. • Built strong customer relationships by tailoring solutions to specific design challenges and delivering hands‑on deployment support. ### MTS @ Sierra Desin Automation Jan 2007 – Jan 2007 • Founding Application Engineer for Olympus (P&R), instrumental in launching the new Noida office from the ground up. • Deployed Netlist‑to‑GDSII flows for customer design teams, ensuring smooth adoption of Olympus tools and methodologies. • Took on start‑up style responsibilities, from infrastructure setup to customer engagement, gaining hands‑on experience in building operations from scratch. • Collaborated with cross‑functional teams (R&D and Marketing)to establish best practices and deliver early success stories that positioned the office for long‑term growth. ### Tech Lead @ NXP Semiconductors India Pvt Ltd Jan 2006 – Jan 2007 | Bangalore Worked on a full chip (90nm) where was responsible for following responsibilities. Top Level : Partitioning, Floor plan, Power grid planning CTS, Timing Physical Verification, Chip Finishing. All the Back End Deliveries to the customers. Working on ARM926(65nm) Hardening, as a Back-End Lead and responsible for Floor plan, CTS and whole netlist to GDSII flow and after that back end support for different Projects and documentation. ### Technical Lead @ NXP Semiconductors India Pvt Ltd Jan 2001 – Jan 2007 | Longmont CO USA Worked in DSG (Design Solution Group), is the Physical Design's SoC design services organization providing Philips product development teams with best in class SoC design services from specification to prototype approval. In which, working as a Physical Design Engineer having responsibilities for RTL2GDS2 design and flow. ### Design Engineer @ Intel Corporation Jan 2000 – Jan 2001 | Folsom CA, USA Worked as Static Timing Analysis engineer for chiplets for the high speed processors ### Design Engineer @ STMicroelectronics Jan 1998 – Jan 2000 | Noida Area, India Ajay was involved in x86 processor design, system-on-chip design, writing device drivers for the Windows 95 / NT and FPGA design. Ajay was working as a physical Design Engineer having following responsibilities. Floor planning and integration of small chiplets Place and Route Physical Verification ECO and timing closure; GDSII database release; ## Education ### National Institute of Technology Kurukshetra Jan 1996 – Jan 1998 ### Jan 1991 – Jan 1995 ### Ludlow Castle No 2 Jan 1983 – Jan 1990 ## Contact & Social - LinkedIn: https://www.linkedin.com/in/amishrax --- Source: https://flows.cv/ajaymishra JSON Resume: https://flows.cv/ajaymishra/resume.json Last updated: 2026-04-07