• Helped port OpenSoC Fabric: Network-On-Chip Generator from Chisel 2 to Chisel 3

• Helped create a hardware implementation of the gem5 MESI Two Level cache coherence protocol simulator in Chisel

• Integrated variable precision DSP blocks on Altera FPGAs into the Rocket Core FPU to increase area efficiency of Rocket generated cores

• Wrote the Verilator Testbench Environment, a peek/poke tester for verilated verilog modules

• Wrote a program for checking in shipments to fulfillment centers for intern project

• Majority of project written in Java

• Worked with Mockito, Spring, and JUnit frameworks as well as DynamoDB

• Taught introductory computer science using Python, Scheme, and SQLite for CS61A

• Taught introductory discrete mathematics and probability for CS70

• Wrote homework, midterm, and final questions