Meta AI & PyTorch Group

Software - Systems Machine Learning (ML)

AI Kernel Development

Employee #7, building dataflow chips from scratch! From conception to successful tapeouts, rooted from published research I worked on at CMU:

• Kernel optimization and SW/HW Co-Design for our custom architecture

• LLVM/MLIR bringup and debug

• RTL design, with both custom and third-party IP

• Energy modeling with real silicon, both in simulation (Joules/Primetime) and silicon back from the fab

• Building PD flows from scratch

Monza, our test chip, is the most energy-efficient reconfigurable chip on the planet, and it can run existing C code:

https://ieeexplore.ieee.org/document/10608171

• Built up our AI accelerator core (effectively an SM) from scratch, focusing specifically on the memory pipeline (scratch and L1D pipelines, memory coalescing, etc.)

• Managed and led design for the cache-coherent CPU cluster cache.

• Contributed to the high performance RISC-V superscalar CPU core, specifically within the ROB and History File.

Worked on the M2/M3/M4 chip CPUs

(Jan. 2019 - May 2019) Research working on ultra-low-power vector processor designs in RISC-V. Advised by Nathan Beckmann and Brandon Lucia. (Published MICRO 2019)

(Sept. 2017 - Dec. 2018) Research on cache partitioning policies on NUCA systems. Advised by Professor Nathan Beckmann.