# Andreas Papaliolios > Vice President of Silicon Engineering at Butterfly. Leading innovation and development of another groundbreaking technology. Location: San Francisco, California, United States Profile: https://flows.cv/andreaspapaliolios Radical innovation leadership across semiconductor and electronic system industry. Strategic/tactical semiconductor/system product, customer, and ecosystem development -- integrating market opportunities with advanced technologies to craft new products, and lead their design and deployment. Proven experience in customer-facing business & relationship development, strategic & product marketing, corporate strategic development, silicon and system architecture, technical design leadership, and manufacturing operations management. Deep technical and market subject-matter expertise in NVM / solid-state storage, IoT edge solutions, AI domain-specific architectures, CMOS circuit technology, and FPGA / SoC platforms for computing, networking, storage, and wireless / mobile / wireline communications. ## Work Experience ### Vice President of Silicon Engineering @ Butterfly Network, Inc. Jan 2026 – Present | Boston, New York, San Francisco ### Vice President Of Engineering @ Pinnacle Semiconductor Jan 2021 – Jan 2026 | Los Altos, California, United States Leading development of new circuit technology and related logic, RF, processor, AI, and memory IP, in manufacturing processes from 40nm to 3nm and smaller. ### Chief Executive Officer @ Janjira Software Jan 2020 – Jan 2024 | Silicon Valley, California, United States Obliterating the vulnerability and annoyance of multi-factor authentication, with applications, tools, and services that seamlessly and securely verify the individual, rather than the device. ### Director, Silicon Platform Strategy & Development @ Renesas Electronics America Jan 2015 – Jan 2019 MCU-based SoC product strategy, architecture, and development, for Internet-of-Things silicon platforms for industrial, health, and machine learning/control. Covering MCUs/CPUs, Memory and Storage Architecture, Comprehensive Cryptography and Security, NVM/Flash, Advanced Power Management, Wireline & Wireless Communications, plus Analog, Video, Mixed-Signal, and Digital systems. Managed global IC design, SoC prototyping in FPGA, relationships with external technology partners. ### VP (Interim) - Silicon/Hardware Product, Technology, & Market Strategy; Design Engineering @ ExecuChip, DFMG, Others Jan 2004 – Jan 2015 Silicon Strategy & Development, IoT - Large IDM Product Strategy, Architecture, & Marketing - Flash Storage Company (interim VP) Product & Technology Strategy - Programmable SoC Company Technology & Market Analysis - Institutional Investment Firm IC Engineering Leadership - Multicore SoC Company (interim VP) Advanced data storage system innovation and development, for VDI and in-memory computing. Silicon product development executive leadership, managing technology and product strategy, design and manufacturing engineering, and early customer engagement. Expert patent & technology analysis, with litigation support. Interim executive leadership. Venture investment technical & financial due diligence. Areas of focus: non-volatile memory technologies (NAND & NOR Flash, PCM, RRAM, MRAM, Ferroelectric, OTP) with related data storage systems; systems-on-chip for storage, networking, communications, and high-performance computing; programmable logic architectures & applications. ### Executive-in-Residence @ Battery Ventures Jan 2002 – Jan 2004 | San Mateo, CA Responsible for developing an investment thesis for semiconductor & electronic system sector. Conducted due diligence on 35+ companies. Advised on market opportunity, technology feasibility, team dynamics, and deal structure. Specialized in advanced memory technologies and (programmable) system-on-chip opportunities. ### Co-Founder, Head of Product Strategy & Architecture @ Semiconductor Startup (GTI) Jan 2000 – Jan 2002 | Sunnyvale, CA Developed technology marketing strategy & tactics, and built initial customer relationships. Led product architecture development for highly-integrated IP-rich field-configurable system-on-chip. Created & nurtured technical and business partnerships with customers to define architecture that serves applications in storage, backhaul, and edge networking, as well as wireless communications. Developed advanced on-chip protocol / interface technology, later adopted by Altera for its 28nm FPGAs. ### Director, Operations & Corp. Quality, SoC Design Engineering @ Xilinx (Triscend) Jan 1997 – Jan 2000 | Mountain View, CA Successfully led custom silicon IC design efforts of Company's first product line, a (hybrid FPGA / MPU / ARM) field-configurable system-on-chip platform product family for networking, computing, communications, and embedded applications. Then led operations & corporate quality, comprising fabless partner ecosystem management, technology evaluation, manufacturing ramp-up of first product family, debug, fab, assembly, test, reliability, and ISO. ### NVM / Flash Design Engineering Manager @ Micron Technology (Micron Quantum Devices) Jan 1994 – Jan 1997 | Santa Clara, CA Designed first flash memory devices shipped in volume by Micron. (As Micron Quantum Devices, a Silicon Valley startup created to introduce flash technology & products to Micron's product mix.) ### IC Design Engineering Lead @ Altera Jan 1992 – Jan 1994 | San Jose, CA IC architecture & design of CPLD, non-volatile memory, and Altera's first-generation FPGA device families, on leading-edge process nodes. ### Sr. IC Design Engineer @ National Semiconductor Jan 1989 – Jan 1992 | Santa Clara, CA Created fundamental innovations in non-volatile Ferroelectric Memory Technology. ### Electronic System Designer @ Aox, Inc Jan 1987 – Jan 1989 ## Education ### MBA in Business Strategy & Management Pepperdine Graziadio Business School ### Master's Degree in Electrical and Electronics Engineering Rensselaer Polytechnic Institute ### Bachelor's Degree in Electrical and Electronics Engineering Rensselaer Polytechnic Institute ## Contact & Social - LinkedIn: https://linkedin.com/in/andreaspapaliolios --- Source: https://flows.cv/andreaspapaliolios JSON Resume: https://flows.cv/andreaspapaliolios/resume.json Last updated: 2026-04-05