Planning and improvement of entire back-end design/CAD methodology for a microprocessor design in order to achieve PPA objectives.
• Improved automation of DCG, ICC2, Extraction, Gatesim, and PT/PT-PX flows and wrote a flow to automate the dispatch of these flows from any starting to ending stage of the flow sequence in order to submit many experiments in parallel.
• Set up gate and rtl-level power analysis and optimization flows using PT-PX and Powerpro.
• Looked into all possible rtl/gate level power saving approaches and implemented the ones which were feasible, including:
• Modified the library cell don’t use list and added new cells.
• Developed a script to find inefficient clock gating based on PT-PX data and disable it in DCG.
• Developed Vt/L swapping script using PrimeTime to swap gates to meet timing and reduce leakage power. Leakage and timing obtained were better than Primetime’s own leakage reduction flow.