# Andrew Demas > CAD Engineer at Condor Computing Location: Mountain View, California, United States Profile: https://flows.cv/andrewdemas 20 years of experience working in high-performance microprocessor design, including CAD programming/methodology, Power Analysis/Optimization, and Circuit/Physical Design/Methodology, both in large organizations and in fast-paced startup environments. Very technical with broad and deep knowledge of semiconductor industry and continuously learning. Excellent communication skills with experience coordinating with and supporting 200+ member design teams and being responsible for critical power rollups. Experienced with the latest FinFET technologies. ## Work Experience ### CAD Engineer @ Condor Computing Corporation Jan 2023 – Present | Sunnyvale, California, United States ### Founder @ Stealth EDA Startup Jan 2022 – Jan 2023 Worked on an EDA tool for PPA data visualization for high-performance semiconductor design. ### Backend CAD Lead Engineer @ Rivos Jan 2021 – Jan 2022 | Mountain View, California, United States Was first backend CAD hire and brought up power and backend analysis tools and methodology from scratch for custom and non-custom design. Drove tool selection, tool setup and flow development, EDA vendor relationships, hiring, and chip signoff. Partially involved with construction tools. Acquired by Meta ### Lead Product Specialist @ Ansys Jan 2020 – Jan 2021 | San Jose, California, United States Product Engineer for PowerArtist and PowerArtist-SC RTL and Gate-level power analysis tools ### Principal Hardware Engineer @ Huawei Technologies Jan 2016 – Jan 2018 | Santa Clara, CA Planning and improvement of entire back-end design/CAD methodology for a microprocessor design in order to achieve PPA objectives. -Improved automation of DCG, ICC2, Extraction, Gatesim, and PT/PT-PX flows and wrote a flow to automate the dispatch of these flows from any starting to ending stage of the flow sequence in order to submit many experiments in parallel. -Set up gate and rtl-level power analysis and optimization flows using PT-PX and Powerpro. -Looked into all possible rtl/gate level power saving approaches and implemented the ones which were feasible, including: -Modified the library cell don’t use list and added new cells. -Developed a script to find inefficient clock gating based on PT-PX data and disable it in DCG. -Developed Vt/L swapping script using PrimeTime to swap gates to meet timing and reduce leakage power. Leakage and timing obtained were better than Primetime’s own leakage reduction flow. ### Senior Power Analysis Engineer @ Apple Inc. Jan 2009 – Jan 2015 | Cupertino, CA In charge of CPU RTL/Gate power analysis and optimization flows and data generation, analysis, and presentation for iPhone CPU chips from the first internally designed iPhone 5 chip to the iPhone 8 and worked with design teams to achieve the power goals. Created robust analysis flows with results reported from many different perspectives in order to discover possible optimizations. Conducted daily power and clock toggling analysis rollups, power optimization flow runs, and full-chip and other special power simulations. Collaborated with EDA vendors to improve tools and supported multiple projects, technologies, and users in parallel internally. Performed accuracy studies for power analysis and final signoffs. Designed an in-house flow for megacell power model creation and reviewed their generation from spice simulations. Developed advanced megacell modeling method to simulate data-dependent power of memories. Updated an in-house flow for doing RTL clock toggling analysis based on a new RTL methodology. Wrote flow for performing full-chip transistor width/length statistics based SOC leakage power estimation. Developed internal flows for performing power optimizations, including a dangling metal check and a megacell Vt/flop swapping flow. Developed Front-End Power Intent Dashboard/Signoff webpages using scripts written in VSILP to gather statistics. Supported UPF negative test regression flow to verify that vendor tools handle all possible design cases. ### Senior CAD Engineer @ PA Semi Jan 2004 – Jan 2007 | Santa Clara, CA - Developed from scratch a Spice-based capacitive coupling noise analysis tool and a full-fledged signal electromigration analysis tool. - Enhanced the noise, Star-RCXT layout extraction and other CAD flows. - Performed full-chip noise/EM simulations and parasitic extractions. - Heavily involved in full-chip design trade-offs between noise, timing, area, power, yield, process scaling, and long-term reliability. - Developed a detailed circuit methodology and the power/signal standard cell and routing templates. - Designed a test chip process control monitor, which measured the speed, leakage, PVT variations, and skew of a process. Performed lab measurements by programming the GPIB interface of test equipment. - Performed flip-flop design and sizing optimization using statistical simulations. ### Circuit Design and Technology @ Sun Microsystems Jan 2000 – Jan 2004 | Sunnyvale, CA - Started working at the age of 16yrs old. - Owner of blocks including one static megacell library, two dynamic megacells, and two place-and-route datapaths. Performed circuit design, analysis, and back-end verification to reach aggressive timing goal and worked with layout designers to implement layout using DFM aware rules. - Created Perl/Tk tool which helps automate flow dispatch and control for ~50 flows. - Performed technology related spice simulations to optimize the metal stack and to evaluate different full-chip routing topologies for area, timing and capacitive/inductive noise. - Set up technology files and limits for EM/IR and noise CAD tools. - Acted as project liaison for EM/IR CAD flow, supporting 100+ users of the tool. Made enhancement requests to CAD group and tested new tool versions, created project specific documentation and technology files, and ran full-chip regressions. - Programming to help the technology characterization and design process, including: o EM/IR and Noise pre-layout checkers. o Automatic cell noise limit generation using Spice. o Critical path simulation helper. o Flow for modifying static timing analysis results based on signal arrival times. ## Education ### Master’s Degree in ECE University of Illinois Urbana-Champaign ### BS in EECS University of California, Berkeley ## Contact & Social - LinkedIn: https://linkedin.com/in/andrew-demas-38994850 --- Source: https://flows.cv/andrewdemas JSON Resume: https://flows.cv/andrewdemas/resume.json Last updated: 2026-04-08