* Leading the compiler and kernels efforts for the MatX architecture, comprising a team of 6 engineers.

* Broadly involved in codesign for many aspects of the architecture and software stack.

* Built a hardware description language embedded in Agda based on distributive categories, with the goal of unifying simulation, formal correctness proofs, and RTL implementation under one programming/proof system.

* Transitioned the compiler/runtime from aging NVidia CuDNN kernel APIs to new more-sophisticated ones.

* Designed a new memory management strategy for the XLA GPU compiler, using a novel MLIR dialect to optimize reference-counting code into statically-allocated and reused buffers.

* Designed the compiler backend and optimization strategy using LLVM and MLIR for a synchronous ML accelerator with a massive-SIMD VLIW programming model, and led a small team for this component.

* Acted as the primary liaison between architecture and software teams to drive convergence between early algorithms and architecture.

* Led the compiler backend team for a synchronous ML accelerator with a highly unconventional design and programming model.

* Contributed to hardware design and some RTL features.