• Updated state machines to enum throughout the design, which has helped the debug process when observing waveforms

• Implemented rate change logic

• Ran and fixed many Lint warnings as well as errors

• Implemented four necessary critical config register blocks and others

• Lane Margining Registers

• Virtual Channel Registers

• Flit-error log Registers

• Resize Bar Registers

• Flit-Mode Debugging Registers

• Created the debug and statistics architecture as well as implemented the entire RTL

• Updated design DL and TL layer for pipe-width=8B and modified inputs to accept 128 bytes from 64 bytes

• >Managed the website for the Alpha Kappa Psi Chapter located at the University of Santa Cruz

• > Tutoring and helping students debug Python Code in CSE 20

• > Ran my own sessions to help out students with assignments and questions