# Anna Polonsky > CPU verification manager at Intel Corporation Location: San Jose, California, United States Profile: https://flows.cv/annapolonsky • 20+ overall years of extensive experience in CPU design and firmware verification, SOC integrations, TFM, DV infrastructure development and technical EPM role. • Successful leadership of SOC, SubSystem, and CPU clusters from the definition stage towards design and verification sign-off before TO • Strong problem solving, leadership and management skills. • Broad system-level view • In-depth knowledge of developing Test Plans, writing/debugging assembly-based tests, coverage methodologies • Hands-on experience in creating TB environments for design verification • Proficiency in design and verification tools with strong debugging skills • x86 CPU architecture • e/Specman, System Verilog, UVM, VCS, ZEBU, C++, Perl, Verdi, GIT, JIRA ## Work Experience ### CPU firmware Verification Manager @ Intel Corporation Jan 2023 – Present | United States Leading teams responsible for end-to-end CPU firmware verification and development of microcode simulator, adopted across CPU clusters. ### IPU Technical Engineering Program Manager @ Intel Corporation Jan 2020 – Jan 2023 Leading the execution of next generation IPU product with 15 IPs across geo. ### CPU Design Verification Manager @ Intel Corporation Jan 2014 – Jan 2020 Leading end-to-end pre-Si verification of Intel CPU clusters - BPU, Instructions decoding, Mid-Level Cache, Power Management ### CPU Design Verification Lead @ Intel Corporation Jan 2009 – Jan 2014 Responsible for CPU Front End cluster verification of Ivy Bridge microprocessor. ### CPU Design Verification Engineer @ Intel Corporation Jan 2003 – Jan 2009 ## Education ### Bachelor’s Degree in Computer Science Technion - Israel Institute of Technology ## Contact & Social - LinkedIn: https://linkedin.com/in/anna-polonsky-1346864 --- Source: https://flows.cv/annapolonsky JSON Resume: https://flows.cv/annapolonsky/resume.json Last updated: 2026-04-13