# Arjun Hary > Software Engineer at Annapurna Labs, AWS Location: San Jose, California, United States Profile: https://flows.cv/arjunhary Have 6 years of experience in firmware development, test automation, failure analysis and performance and power analysis on a wide array of NAND flash based products (SSDs and USB) Specialties: •Languages: C •Tools: LabVIEW, JTAG Debugging, Protocol analyzers (USB and PCIe), Logic Analyzers, Microsoft Office and EXCEL VB scripting •Scripting Languages: python •Storage Protocols : USB, SATA and PCIe •Embedded OS : Designware ARC MQX ## Work Experience ### Software Engineer @ Annapurna Labs Jan 2019 – Present ### Firmware Engineer @ zGlue Jan 2017 – Jan 2019 | San Francisco Bay Area ### Sr.System Design Engineer @ SanDisk Jan 2013 – Jan 2017 | Milpitas,California • Currently working on SOC and PCB validation for an enterprise storage product Developed firmware for an early stage SOC to exercise the interface between controller and NAND Enhanced firmware to do writes/reads to the NAND XDL in parallel on multiple channels Developing a LabVIEW based test platform to test the NAND, DRAM and SPI interfaces in the SOC under various environmental conditions Sr.System Design Engineer: Custom PCIe Product • Developed ARM Firmware code for Xilinx ZC706 with ZynQ 7Z045 for Custom PCIe product Developed test functions for ARM Cortex A9 bare metal application Developed basic write, read and erase functions for custom PCIe device under test Developed test cases for all supported PCIe power saving modes • Developed and maintained an automated product characterization platform for a custom PCIe product: Developed a LabVIEW based automation system with Agilent N6705B power analyzer, temperature chamber, PICO temperature logger and custom PCIe product Developed performance test cases exercising various access patterns and queue sizes Developed power saving test cases to measure power in all supported low power PCIe states Developed thermal throttling test cases to check the effect of temperature on performance Responsible for running bi-weekly regressions and sending an automated report to team Debugged various performance, power saving and device boot up issues with help of lecroy protocol analyzer , JTAG and PCIe trace parsers Developed a simple PCIe trace post processor in python Created and maintained test plan for automated regression ### Firmware Engineer @ SanDisk Jan 2010 – Jan 2013 | Milpitas,California • Developed Firmware and worked on modifying LED behavior for SanDisk Memory vault product • Multi Partition USB Product: o Developed Firmware for Removable- Removable and Removable-CDROM configurations and implemented CDROM commands as per MMC spec o Designed a test plan and implemented all test cases • Flash Management Layer for SSD: o Worked on a new Flash Management Layer. Developed APIs for Flash Read, Write , Erase and Logical to physical Address conversion o Modified existing platform and Maintained the new platform for whole project o Designed a test plan and tested the new flash management layer for Multi bank and Multi die configurations o The new Flash management layer showed significant performance improvements over the existing one • Responsible for Design, Implementation, Testing and Release of ROM for a proprietary product. • Fault Detection and Debugging for SSD: o Designed and Implemented a feature in case of special fault cases , all the memories and registers are dumped to flash and later retrieved for debugging o Integrated the new code with existing SSD product platforms o Developed the whole test plan and automated the testing of fault detection system for multiple product configurations • WHQL Compliance for USB: o Created the WHQL setup in the lab o Ran tests and Fixed all SCSI and protocol failures on USB 2.0 products ### Graduate Research Assistant at Autonomic Computing Lab @ University of Arizona Jan 2008 – Jan 2010 Accelerated Discovery Cycles: The aim of the project is to dynamically couple and autonomically configure workflows. These workflows model the interactions between the various components in the Biosphere 2 facility. •Created a distributed MATLAB actor using the XMLRPC client-server model •Modified the open source Kepler project to incorporate Distributed Matlab actors •Integrated Data Turbine with the Kepler Project to enable real time Data streaming •Modified the existing Kepler project to dynamically change parameters of the workflow •Built a Autonomic Fault Tolerant system for workflows with checkpointing •Integrated Kepler with Autonomia to automate the control of different parameters in the workflow based on policies •All the development was done in Java on eclipse platform ### Graduate Teaching Assistant @ University of Arizona Jan 2008 – Jan 2008 Computer Architecture (Graduate Level): Responsible for handling Lab sessions. Lectured the class on the Superscalar, MIPS and dinero simulators. Involved in preparation and grading of assignments and exams ### Graduate Research Assistant at Reconfigurable Computing Lab @ University of Arizona Jan 2007 – Jan 2008 Non Equispaced FFT • Designed, developed and verified synthesizable RTL codes for first two stages of NFFT algorithm (Kernel Rolloff correction and FFT) • Designed and implemented FSM and High level RTL for the Kernel Rolloff correction • Implemented the FFT stage using the Xilinx FFT core in continuous streaming mode • Implemented DDR2 memory interface at 200MHz using the Xilinx Memory Interface coregen in a Xilinx ML501 board and tested the interface using Xilinx Chipscope ### Programmer Analyst Client @ Cognizant Technologies Solutions Ltd Jan 2006 – Jan 2007 ACE Hardware Project: Business Priorities Development (BPD) · Developed ASP pages for the store system · Developed COBOL and Mainframe programs for the retail system · Designed and Developed online screens for Mainframe · Other responsibilities included maintenance of DB2 and IMS databases and batch Job Scheduling ## Education ### Master of Sciences in Electrical and Computer Engineering University of Arizona ### Bachelor of Engineering in Electrical and Electronics Engineering Government College of Technology (GCT) ## Contact & Social - LinkedIn: https://linkedin.com/in/arjun-hary-0119517 --- Source: https://flows.cv/arjunhary JSON Resume: https://flows.cv/arjunhary/resume.json Last updated: 2026-04-11