# Arun Jangity

> Director Silicon Design Engineering

Location: United States, United States
Profile: https://flows.cv/arunjangity

Driven by First Principles and Vertical Integration

## Work Experience
### Director Silicon Design Engineering @ AMD
Jan 2025 – Present | San Jose, California, United States

### Director, Silicon Design Engineering @ Altera
Jan 2025 – Jan 2025

### Director FPGA Design @ Intel Corporation
Jan 2016 – Jan 2025 | San Jose, California, United States

### Sr Manager IP Design @ Altera
Jan 2014 – Jan 2015 | San Jose, CA
FPGA core fabric

### Sr. Manager Engineering @ AppliedMicro
Jan 2009 – Jan 2014 | Sunnyvale, CA
Responsible for the implementation of high speed processors using ASIC and semi-custom physical design methodology

### Member of Technical Staff @ Cswitch
Jan 2006 – Jan 2009
Responsible for >2GHz high speed interconnect for an custom FPGA. 1GHz SRAM design in 90nm. Was also part of the circuit team to model and validate the timing for a complex FPGA

### Silicon Engineering @ Montalvo Systems
Jan 2005 – Jan 2006
Part of the circuit methodology group tasked to implement the best energy efficient techniques available.

### Lead, Product Development @ PMC-Sierra is now Microsemi
Jan 1998 – Jan 2005
High performance circuit design and datapath implementation for high-end server class MIPS processors


## Education
### BS in EECS
University of California, Berkeley

### Homestead High School


## Contact & Social
- LinkedIn: https://linkedin.com/in/arun-jangity-55bba7

---
Source: https://flows.cv/arunjangity
JSON Resume: https://flows.cv/arunjangity/resume.json
Last updated: 2026-04-13