PROFILE: * Technical Leadership at Cisco and Intel for 3 years for Catalyst 6500, Set-top box and Print Server group.
Experience
2020 — Now
2020 — Now
Santa Clara, CA
Working on next generation firewall products based on chassis architecture. Key components include I2C, Tomahawk3, Jericho2, udev, HSUART, Python, x86, CPLD, multi-DP bringup, bringup scripting, BCM Ramon based fabric, PXE boot, data path monitoring/logging and recovery, cmd injection vulnerability fixes, checkpoint boot sequence using CPLD support, gearbox init sequence changes, solving manufacturing diagnostics issues, GRUB configs, Linux kernel and drivers, telemetry based AI signature support, LED streaming, image construction, emulation, NVME drive hot plug etc.
2017 — 2020
2017 — 2020
San Jose, CA
Acquired into Brocade Fibrechannel Switching Business Unit as part of Brocade acquisition by Broadcom. Delivered RESTful backend modules for trunking, port buffers and port counters. Also, delivered inter-chassis links at 64G between switches using QSFP form factor optics. Developed shell scripts for a bolted setup for Auto-speed negotiation and snake traffic/thermal tests. Working on a hardware synchronized clock (PTP) in the fabric within a data center and across data centers.
2012 — 2017
2012 — 2017
San Jose, CA
* Work on Fiber Channel SAN switch. Major project include Flex port post-silicon ASIC verification (F/E/C port, FEC, Brocade trunking, credit management, 2/4/8/16Gbps speeds). Test cases were developed using bash and awk shell scripts and interface into the peek/poke memory sub-system. Port driver state machine development for the cobra ASIC. Name of state machines include LKSM, PHYSM, UPSM and FEC. Also worked on TCAM entry programming, FC personality registers & ACL for forwarding of frames. Working with engineers cross site in US and India for bug fixing in the ASIC driver layer and sanity regression test suite development. JTAG debugger used was BDI3000. Used C-model for debugging internal asic FC frame processing.
* Implemented & verified emulation based bring up for chip initialization code, MSI interrupt handler for a new ASIC, as well as ASIC driver bringup on a new pizza box/chassis, debugging & bug fixing, HA on pizza box with zero frame loss, PCIe error interrupt handling and unit tests for INIT/INTERRUPT code with error injection.
* Responsible for driver for PCIe ASIC interface/DMA operations and Transmit queue block in the FC chipset.
* Delivered use of higher order VC's to minimize the impact of over subscription on multi-chip high port density pizza box switch.
* Implemented FC QOS a.k.a csctl for creating high, medium and low csctl ranges which are mapped to the VC mapping to prioritize packet flow in the switch.
2007 — 2012
2007 — 2012
San Jose, CA
Software Development for next generation Catalyst 6500 switches for Campus & Data Centers. Specializing in area of power management, thermal and cooling control as well as work on porting system management IOS code on Nexus 7K platforms & board bring up of NXOS kickstart ( a Linux derivative) on Simics P4080DS board and profiling/analysis of network virtualization methods with KVM hypervisor.
High availability related development for control plane applications when migrating from 2 SUP SSO model to 4 SUP SSO model.
Board bringup of IOS on x86 Gladden CPU as well as developing 2 wire drivers using MMIO and I/O mapped I/O for FPGA's as well as SM bus, I2C and MDIO buses.
Architected/Design the framework for Fabric Extender for system management of Cat2K from Cat6K.
2006 — 2007
2006 — 2007
Linux,C, C++ engineer specializing in embedded products viz. settops, IP TV encoders, ATCA switches, wireless car alarm device. Major project include an embedded custom MIB, Javascript/ASP based web front end development using NuDesign SDK.
Education
Kansas State University
MS
National Institute of Technology, Hamirpur
BTech
GREMS, Baroda, Gujarat
High School
SPV, New Delhi, India