# Atul Sabharwal > Principal Engineer at Palo Alto Networks Location: San Jose, California, United States Profile: https://flows.cv/atulsabharwal PROFILE: * Technical Leadership at Cisco and Intel for 3 years for Catalyst 6500, Set-top box and Print Server group. Responsible for design, development, code reviews, debugging, reviewing documents and test plans, driving project schedule, reviewing/answering MRD/PRD documents, bug scrubs and prioritizing defects, clarifying/dropping requirements, mentoring junior engineers, planning tasks and estimated schedules etc. Led small teams of 4 to 8 people and worked closely with them. * Embedded Software engineer with twenty years of experience developing Switching, Test & Measurement and Consumer Electronics products * Liaison/collaboration experience with vendors and cross functional teams in different organizations. * Worked on Brocade customized FC/FCOE ASIC(s) bring up and driver development for Cobra, Cobra2, Condor4 & Goldeneye4 for last 5.5 years. SOFTWARE EXPERTISE: Compilers: gcc/g++ Architectures: PowerPc (MPC4080/3041/T-series/8540/870/852) & Strong Arm (SA 110), Xscale (IXP420), x86 (Gladden, Pentium, Centrino, 486). Hypervisor: Freescale Hypervisor, KVM Version Control: git, CVS, Clearcase, SVN O/S: Linux (MontaVista, RedHat & Gentoo), Cisco Nexus O/S, Brocade FOS/NOS, Solaris, IOS. Documentation: MS Word, Office, Excel, PowerPoint, Google docs. Miscellaneous: bash, perl, lex, yacc. ## Work Experience ### Principal Engineer @ Palo Alto Networks Jan 2020 – Present | Santa Clara, CA Working on next generation firewall products based on chassis architecture. Key components include I2C, Tomahawk3, Jericho2, udev, HSUART, Python, x86, CPLD, multi-DP bringup, bringup scripting, BCM Ramon based fabric, PXE boot, data path monitoring/logging and recovery, cmd injection vulnerability fixes, checkpoint boot sequence using CPLD support, gearbox init sequence changes, solving manufacturing diagnostics issues, GRUB configs, Linux kernel and drivers, telemetry based AI signature support, LED streaming, image construction, emulation, NVME drive hot plug etc. ### Principal Engineer @ Broadcom Limited Jan 2017 – Jan 2020 | San Jose, CA Acquired into Brocade Fibrechannel Switching Business Unit as part of Brocade acquisition by Broadcom. Delivered RESTful backend modules for trunking, port buffers and port counters. Also, delivered inter-chassis links at 64G between switches using QSFP form factor optics. Developed shell scripts for a bolted setup for Auto-speed negotiation and snake traffic/thermal tests. Working on a hardware synchronized clock (PTP) in the fabric within a data center and across data centers. ### Sr. Staff Software Engineer @ Brocade Jan 2012 – Jan 2017 | San Jose, CA * Work on Fiber Channel SAN switch. Major project include Flex port post-silicon ASIC verification (F/E/C port, FEC, Brocade trunking, credit management, 2/4/8/16Gbps speeds). Test cases were developed using bash and awk shell scripts and interface into the peek/poke memory sub-system. Port driver state machine development for the cobra ASIC. Name of state machines include LKSM, PHYSM, UPSM and FEC. Also worked on TCAM entry programming, FC personality registers & ACL for forwarding of frames. Working with engineers cross site in US and India for bug fixing in the ASIC driver layer and sanity regression test suite development. JTAG debugger used was BDI3000. Used C-model for debugging internal asic FC frame processing. * Implemented & verified emulation based bring up for chip initialization code, MSI interrupt handler for a new ASIC, as well as ASIC driver bringup on a new pizza box/chassis, debugging & bug fixing, HA on pizza box with zero frame loss, PCIe error interrupt handling and unit tests for INIT/INTERRUPT code with error injection. * Responsible for driver for PCIe ASIC interface/DMA operations and Transmit queue block in the FC chipset. * Delivered use of higher order VC's to minimize the impact of over subscription on multi-chip high port density pizza box switch. * Implemented FC QOS a.k.a csctl for creating high, medium and low csctl ranges which are mapped to the VC mapping to prioritize packet flow in the switch. ### Sotware Engineer Level IV @ Cisco Corporation Jan 2007 – Jan 2012 | San Jose, CA Software Development for next generation Catalyst 6500 switches for Campus & Data Centers. Specializing in area of power management, thermal and cooling control as well as work on porting system management IOS code on Nexus 7K platforms & board bring up of NXOS kickstart ( a Linux derivative) on Simics P4080DS board and profiling/analysis of network virtualization methods with KVM hypervisor. High availability related development for control plane applications when migrating from 2 SUP SSO model to 4 SUP SSO model. Board bringup of IOS on x86 Gladden CPU as well as developing 2 wire drivers using MMIO and I/O mapped I/O for FPGA's as well as SM bus, I2C and MDIO buses. Architected/Design the framework for Fabric Extender for system management of Cat2K from Cat6K. ### Software Engineer @ Oxford International Jan 2006 – Jan 2007 Linux,C, C++ engineer specializing in embedded products viz. settops, IP TV encoders, ATCA switches, wireless car alarm device. Major project include an embedded custom MIB, Javascript/ASP based web front end development using NuDesign SDK. ### Embedded Software Engineer @ Tektronix Jan 2004 – Jan 2006 | Hillsboro, Oregon Software engineer working on Linux based board bringups with u-boot &Redboot loaders for logic analyzers and oscilloscopes. Working with PPC & Xscale processors. Major projects were board bring up, manufacturing/field software/FPGA upgrades, configuration database management and DDR memory controller bring up for PPC 885 microprocessor. Serial drivers developed included MDIO, SPI for Broadcomm switch chip interface with Xscale processor. JTAG Debugger used was BDI2000. ### Senior Software Engineer @ Intel Corporation Jan 1996 – Jan 2004 | Hillsboro, Oregon Software engineer working on server grade Linux and embedded devices viz. print servers, settops, laptops, wireless, LKML. Major projects include boot loader for x86 for Linux, test harness for embedded TCP/IP stack, forced unmount of file system and process/thread monitoring under Linux, ASIC driver and verification for 16550 UART, 8051 micro-controller, heartbeat and iptables based traffic metering. ### Student Network Administrator @ Kansas State University Jan 1995 – Jan 1996 | Manhattan, Kansas Managed windows desktop, novell netware network and print servers for College of Business. Involved in evaluating migration from Novell Netware to Windows NT. ### Summer Intern @ UOP Jan 1995 – Jan 1995 Worked on security and logging solution for research documents in corporate library using Novell Netware/Windows SDK & ODBC. ### Technical Marketing Engineer @ TATA Honeywell, Pune, India Jan 1993 – Jan 1994 | Pune, India Involved in competitive analysis of software/hardware architectures for Honeywell TDC3000 and US X digital process control and monitoring system. Focus was on computer networks, inter-connectivity of plant and management network etc. ### Summer Intern @ Wipro Infotech Ltd Jan 1992 – Jan 1992 dBase programmer for materials inventory control system. ### Summer Intern @ Indian Oil Corporation Limited Jan 1991 – Jan 1991 | New Delhi Implemented a prototype Ticket Booking/Employee Allowance system in PASCAL. ## Education ### MS in Computer Science Kansas State University ### BTech in Computer Science National Institute of Technology, Hamirpur ### High School in Science GREMS, Baroda, Gujarat ### Secondary School in Science SPV, New Delhi, India ## Contact & Social - LinkedIn: https://linkedin.com/in/atul-sabharwal-2901564 --- Source: https://flows.cv/atulsabharwal JSON Resume: https://flows.cv/atulsabharwal/resume.json Last updated: 2026-04-12