• Created Perl scripts and custom reports to perform STA on chip level timing interfaces

• Analyzed timing violations and created timing ECOs to fix setup and hold violations

• Achieved timing closure on a 28nm design with multiple PVT corners using MCMM analysis

• Created STA scripts and developed timing models to enable early chip level timing analysis of a 100 million gate 40nm design with over 400 clock domains and 20 timing modes

• Performed chip level STA on timing critical data interfaces and recommended logic changes

• Created STA scripts and developed timing models to enable early chip level timing analysis of a 100 million gate 40nm design with over 400 clock domains and 20 timing modes

• Performed chip level STA on timing critical data interfaces and recommended logic changes

* Led a 20-member global design team developing a 7x7mm SoC chip in 40nm technology

* Defined chip specifications in consultation with chip architects and marketing team

* Coordinated design teams from four global design centers on IP development, chip integration,

verification, STA, DFT, layout, package and firmware development

* Provided technical leadership in various aspects of IC design to ensure seamless integration

* Tracked project-wide deliverables and drove rapid bug fixes and issue resolution

* Performed STA, resolved timing issues with physical design team and achieved

timing closure