# Catherine C.

> SoC Design Engineer - Intel Corporation

Location: Sunnyvale, California, United States
Profile: https://flows.cv/catherinec

•	Senior IC design engineer with over 15 years experience in SOC devices
•	Leader of global cross-functional design teams with 2 successful chip tape-outs 
•	Experience working closely with external customer design teams
•	Hands on experience in all aspects of ASIC design:  design specification, RTL, verification, synthesis, static timing analysis and closure, formal verification and design for test

## Work Experience
### SoC Design Engineer @ Intel Corporation
Jan 2015 – Present | San Francisco Bay Area

### IC Design - SMTS @ Altera
Jan 2013 – Present | San Francisco Bay Area

### IC Design @ Broadcom Inc.
Jan 2013 – Jan 2013 | San Francisco Bay Area
• Created Perl scripts and custom reports to perform STA on chip level timing interfaces 
• Analyzed timing violations and created timing ECOs to fix setup and hold violations
• Achieved timing closure on a 28nm design with multiple PVT corners using MCMM analysis

### Product Design @ PMC-Sierra is now Microsemi
Jan 2011 – Jan 2012 | Vancouver, Canada Area
• Created STA scripts and developed timing models to enable early chip level timing analysis of a 100 million gate 40nm design with over 400 clock domains and 20 timing modes 
• Performed chip level STA on timing critical data interfaces and recommended logic changes
• Created STA scripts and developed timing models to enable early chip level timing analysis of a 100 million gate 40nm design with over 400 clock domains and 20 timing modes 
• Performed chip level STA on timing critical data interfaces and recommended logic changes

### Project Lead, ASIC Design @ ViXS Systems Inc.
Jan 2009 – Jan 2011
* Led a 20-member global design team developing a 7x7mm SoC chip in 40nm technology
* Defined chip specifications in consultation with chip architects and marketing team
* Coordinated design teams from four global design centers on IP development, chip integration, 
  verification, STA, DFT, layout, package and firmware development
* Provided technical leadership in various aspects of IC design to ensure seamless integration
* Tracked project-wide deliverables and drove rapid bug fixes and issue resolution
* Performed STA, resolved timing issues with physical design team and achieved 
  timing closure

### Sr. Product Design Engineer @ PMC Sierra Inc.
Jan 2001 – Jan 2009
Chip Lead
• Developed static timing and closure strategy for a 65nm 27x27mm design with dual-voltage ARM core 
   and 16 scan clock domains
• Designed a padring for an external customer with PCIE, DDR2, Gigabit Ethernet and USB interfaces
• Provided technical support to external customers with ATPG, functional and scan mode timing, layout 
   and packaging methodologies
• Managed offshore design teams (located in India), resolving technical issues promptly
• Integrated and verified a 5-port USB PHY external IP with a customer’s USB controller
• Implemented ECOs for both functional and timing bugs

Static Timing Analysis 	
• Converged timing on subsystems and chips of up to 50M gates in size with cross-clock domains,
   multiple voltage domains and multiple modes in 65nm and older technologies
• Designed chip-level STA strategies including design partition; synthesis constraints
• Created timing constraints, generated timing analysis and report parsing scripts
• Analyzed and resolved violations with layout by adjusting place/route and clock tree structures, 
  balancing clock skew, determining crosstalk aggressors and resizing cells

RTL design 
* Designed a programmable SONET/SDH timeslot interchange block
* Designed a SATA/SAS out-of-band signal detection and control circuit
* Chip-level module integration including external IP, mixed language designs and analog models
* Experience with ARM v7 bus interfaces and high-speed I/O (DDR2, PCIe, Gigabit Ethernet)

Synthesis 
* Synthesized RTL designs with Synopsys Design Compiler and Cadence RTL Compiler
* Specified constraints on clock frequency, transition, drive and load in SDC format

Functional Verification 
* Integrated a Gigabit Ethernet test widget with a Specman testbench;
   resolved mixed language (VHDL and Verilog) probing issues
* Designed testbenches in Tcl to verify connectivity between a digital control block and a PLL
* Designed a model to verify a Fibre Channel automatic port reconfiguration mechanism

### IC Designer @ Agilent Technologies
Jan 2000 – Jan 2001
* Re-synthesized an RTL design from 0.35um to 0.18um TSMC and Chartered processes
* Designed a Verilog and C testbench to verify USB transfers in an SoC
* Performed artwork verification of ASICs using CheckMate and ChipBuster


## Education
### Bachelor of Applied Science - BASc in Computer Engineering
The University of British Columbia


## Contact & Social
- LinkedIn: https://linkedin.com/in/catherinechan12yrasicdesign

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Source: https://flows.cv/catherinec
JSON Resume: https://flows.cv/catherinec/resume.json
Last updated: 2026-04-13