# ChangSoo Kim

> Founder, CEO at AiM Future / SilicoNeuro

Location: Morgan Hill, California, United States
Profile: https://flows.cv/changsoo

Experienced Principal Engineering Manager and Program manager with a demonstrated history of delivering many IPs and chips in the consumer electronics industry. 

Specialties: Microprocessor/DSP/RISC processors design. Processor hardware architecture, low power design, CNN/DNN accelerator HW IP development

## Work Experience
### Founder, CEO @ AiM Future
Jan 2020 – Present | Seoul, South Korea
AiM Future is a spin-off company from LG Electronics based-in Seoul, Korea. 
SilicoNeuro, Inc is US-based entity focusing on research & sales/marketing/biz development for North America markets
Providing silicon-proven, scalable, configurable inference & training NPU IP(running at 1GHz with TSMC 28nm process) for automotive, consumer electronics, IoT, and other applications
Having DDK, quantization-aware training, auto-labeling, spiking neural networks and TF-XLA compiler technologies.

### Principal Engineer @ LG Electronics
Jan 2013 – Jan 2020
Micro-architecture/implementation on L3 cache controller and other modules for mobile AP(application processor) chip using TSMC 28/16nm and INTEL 10nm technologies. Guide Design Methodology & CAD tool environment setup. Leading & Managing RTL implementation team. Project Leader for System Level Cache project. Timing Optimization on RISC-V processors used in Neuro-morphic Processor for 600MHz target. Program Manager on Neuromorphic Computing project as well as leading RTL implementation team for developing 1GHz+ RISC-V processor-based SoC IP targeting CNN/DNN applications using SegNet, LeNet, PVANET, and other neural network algorithms. Engaging in architectural discussion to deliver 2nd generation neural engine IP for SoC chip.

### Staff Product Engineer @ Cadence Design Systems
Jan 2010 – Jan 2013
Design/Implementation/Verification/Power Analysis/Low Power implementation/DFT on DDR PHY, WideIO PHY using various technologies including TSMC/GF/ST 28nm and below.

### Chief Hardware Architect @ Virage Logic
Jan 2009 – Jan 2010
Architect/Design/Verification of XY packing/unpacking module in ARC AS221, dual-core systems.
High level architect and implementation ARC601 processor
Implemented dual 32x16 XMAC hardware.
Perform synthesis and functional verification.
Hardware architecture on CMEM and XMAC for new instructions

### CTO @ Kairos Logic
Jan 2007 – Jan 2008
logic design  & verification of video-oriented 32bit DSP processor called EVE(Enhanced Video Engine)
Instruction-set development for H.264 application

### Sr. Logic Design Engineer @ Cradle Technologies
Jan 2001 – Jan 2007
Perform logic design for 32bit RISC processor and DSP engine using Verilog.
Perform Functional Verification by VCS and Logic synthesis by RC.
Perform Static timing analysis.(Pearl, PKS)
Perform Power Analysis(PowerTheater)

### Sr. IC Design Engineer @ Texas Instruments
Jan 2000 – Jan 2001
Worked on E2ICE(Enhanced Embedded ICE) module of ARM925T V2.5 macro module which is incorporated in OMAP.
Perform RTL coding and verification by Modelsim.
Power analysis and optimization of ARM9EJS core, ARM925T using Power Compiler
Compiler Code coverage analysis is performed on whole design using Navigator

### Staff Engineer @ Silicon Magic
Jan 1997 – Jan 2000
Implemented Vector Processor called MBP.
ISA definition and development for MBP.
Performed logic design and functional verification.
Performed circuit design of custom Datapath cells for low power such as l6bit Adders, MUXs, TSPC(True Single Phase Register) registers using 0.25um TSMC library.
Worked on 32bit REX(RISC Execution Unit) processor’s performance improvement

### Design Manager @ Samsung Semiconductor
Jan 1988 – Jan 1997
Worked on 0.5um custom macro cell library design used for Floating-point unit and logic blocks in MSP(Multimedia Signal Processor)
Performed 256x256 high-speed Wallace tree multiplier circuit design and functional verification with Verilog, TimeMill, and critical path analysis by Pathmill.
Supervised layout team to floorplan, integration, and verification of 256x256 multiplier for execution unit.
lEEE754 Floating point unit functional verification and static timing analysis by Pathmill
Developed macro cells using data-path generator(1994.2 - 1994.11)
co-developed Samsung’s 0.8um macro cell ASIC library using Mentor Graphics GDT tools with VLSI Libraries(1993.8 - 1994.2)
Logic and Circuit design of various chips for voice/speech synthesiszer, OSD ICs(1988.4 - 1993.7)


## Education
### BSEE in Electrical Communications
Kwangwoon University


## Contact & Social
- LinkedIn: https://linkedin.com/in/changsoo-kim-1699b11

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Source: https://flows.cv/changsoo
JSON Resume: https://flows.cv/changsoo/resume.json
Last updated: 2026-04-13