• Managed multiple IP teams to develop, verify, and deliver updates and new features.

• Communicated and collaborated with the SOC team to ensure successful and smooth tapeout of various SOCs.

• Led the team in collaboration with the DSP team to enhance the LDPC engine, supporting new NAND generations with higher correction performance and significantly reduced area and power per GB/s throughput.

• Defined and designed a new generation of Flash Controller IP, offering flexibility to support new NAND features without re-spin, and scalability to meet the speed requirements of each new NAND generation.

• Optimized NVMe IP to reduce area and power, ensuring scalability to meet the needs of new PCIe generations, and flexibility to support new features in NVMe/OCP/MFND specifications.

• Defined an accelerator to manage data buffers between NVMe and Flash Controller IP, distributing data based on firmware algorithms for programming data to NAND and garbage collection.

• Designed an accelerator to offload routine CPU tasks in processing read and write commands, utilizing a scalable custom processor design.

• Communicated with various customers to gather and summarize requirements and trends, ensuring internal designs meet customer expectations.

• Designed Reed-Solomon code for HDD controller projects.

• Sole designer of high-speed BCH encoder/decoder, starting from a primitive polynomial.

• Developed scripts to automatically generate BCH encoder RTL code with varying levels of parallelism and correction power, ensuring flexibility for different SOC requirements in minimal time.

• Defined architecture and implemented RTL for the Error Correction Unit with an LDPC engine for SSD controllers.

• Defined and implemented both the RTL and verification plan for a RAID solution in SSD controllers.

• Conducted LINT checks, CDC checks, and used Design Compiler to ensure high-quality delivery.