# ChengKuo Huang

> Senior Director, Design Engineering @ Marvell Technology | RTL design, IP design, Architecture

Location: Los Altos, California, United States
Profile: https://flows.cv/chengkuo

At Marvell Technology, leadership in design engineering blends with a deep-seated expertise in Error Correcting Codes to drive cutting-edge developments in SSD controllers. Our team has been pivotal in enhancing LDPC engines and optimizing NVMe IPs, focusing on area and power reduction while scaling to meet progressive speed requirements.

Collaborating closely with SOC and DSP teams, we have ensured successful tapeouts and introduced a flexible Flash Controller IP—characterized by its adaptability and scalability. This strategic direction not only supports new NAND generations but also aligns with our mission to deliver high-performance, cost-effective solutions to the market.

## Work Experience
### Senior Director, Design Engineering @ Marvell Technology
Jan 2023 – Present
- Managed multiple IP teams to develop, verify, and deliver updates and new features.
- Communicated and collaborated with the SOC team to ensure successful and smooth tapeout of various SOCs.
- Led the team in collaboration with the DSP team to enhance the LDPC engine, supporting new NAND generations with higher correction performance and significantly reduced area and power per GB/s throughput.
- Defined and designed a new generation of Flash Controller IP, offering flexibility to support new NAND features without re-spin, and scalability to meet the speed requirements of each new NAND generation.
- Optimized NVMe IP to reduce area and power, ensuring scalability to meet the needs of new PCIe generations, and flexibility to support new features in NVMe/OCP/MFND specifications.
- Defined an accelerator to manage data buffers between NVMe and Flash Controller IP, distributing data based on firmware algorithms for programming data to NAND and garbage collection.
- Designed an accelerator to offload routine CPU tasks in processing read and write commands, utilizing a scalable custom processor design.
- Communicated with various customers to gather and summarize requirements and trends, ensuring internal designs meet customer expectations.

### Director SSD IP Design @ Marvell Technology
Jan 2019 – Jan 2023

### Design Manager / Sr. Staff Design Engineer @ Marvell Technology
Jan 2012 – Jan 2019 | Santa Clara, California

### Staff ASIC design engineer @ Marvell Technology
Jan 2006 – Jan 2012 | Santa Clara, California
- Designed Reed-Solomon code for HDD controller projects.
- Sole designer of high-speed BCH encoder/decoder, starting from a primitive polynomial.
- Developed scripts to automatically generate BCH encoder RTL code with varying levels of parallelism and correction power, ensuring flexibility for different SOC requirements in minimal time.
- Defined architecture and implemented RTL for the Error Correction Unit with an LDPC engine for SSD controllers.
- Defined and implemented both the RTL and verification plan for a RAID solution in SSD controllers.
- Conducted LINT checks, CDC checks, and used Design Compiler to ensure high-quality delivery.


## Education
### Master's Degree in Electrical Engineering
University of Southern California

### Bachelor's Degree in Electrical Engineering
National Chiao Tung University


## Contact & Social
- LinkedIn: https://linkedin.com/in/chengkuo-huang-21813510

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Source: https://flows.cv/chengkuo
JSON Resume: https://flows.cv/chengkuo/resume.json
Last updated: 2026-04-13