# Chi-Kai Chien > VP/CTO Leader | AI, Data & SaaS Innovation | Team Builder Location: San Francisco Bay Area, United States Profile: https://flows.cv/chikai I’m a hands-on senior engineering and product leader with a track record of aligning business goals with product strategy and execution. I’ve built and scaled high-performing teams across startups and large tech companies, driving both innovation and operational excellence. I thrive at the intersection of technology, product, and business, translating ambitious visions into concrete results by enabling teams to deliver at scale. Whether it’s leading AI- and ML-driven product transformations, building enterprise-grade platforms, or growing teams from a handful of engineers to hundreds, I focus on creating the conditions for teams to succeed. Highlights: • Led engineering, product, and data teams at startups and global tech companies. • Drove enterprise readiness, CI/CD, observability, and automated testing to scale systems reliably. • Initiated transition from ML- and genAI-enabled products to AI-native architectures. • Built data and analytics platforms to improve engagement, monetization, and business decisions. • Scaled operational businesses and SaaS platforms while maintaining compliance and efficiency. • Recruited and developed top-tier talent, fostering high-performing, accountable teams. I’m passionate about empowering teams to achieve more than they thought possible, translating complex technical challenges into business impact, and delivering products that delight users and drive growth. ## Work Experience ### VP, Engineering @ Authorium Jan 2026 – Present | San Francisco ### VP, Engineering @ Pave Jan 2025 – Jan 2025 | San Francisco, CA Led Product & Platform Engineering, Data, and Security/IT teams, partnering with GTM, Product, and Marketing to align the roadmap with company vision and drive step-change growth in the sales pipeline. • Strengthened enterprise readiness—enhancing performance, uptime, observability, incident response, CI/CD, and automated testing. • Advanced ML- and genAI-enabled features; piloted AI-native architecture through an agent proof of concept using Google ADK and LangGraph. • Managed R&D budget across headcount, SaaS, and infrastructure; maintained spend under budget through disciplined cost management. • Elevated security posture, achieving SOC 2 and ISO 27001 certifications. • Expanded and developed the management layer, introducing structured feedback, performance reviews, and career progression systems. ### VP, Engineering @ Calm Jan 2023 – Jan 2025 | San Francisco Bay Area Led Platform, Product Infrastructure, Data Science, and Data Engineering teams to deliver scalable platform and data capabilities powering personalized experiences and business growth. • Built embedding-based recommendation systems and delivered genAI video/audio proof of concepts. • Developed ML models predicting renewal rates and user behavior, helping inform retention and monetization strategies. • Implemented modern authentication implementation (SSO & MFA) and optimized content delivery pipelines. • Migrated data pipelines from Redshift to Databricks, cutting compute costs in half and improving run times 4×. • Partnered with Product and Growth teams to design experiments, improve engagement, and support revenue goals. • Built data products for payers and employers (feeds and dashboards) and unified data delivery across Lifecycle, User Acquisition, and Finance teams to ensure insights were accessible and actionable company-wide. ### Founder & CEO @ Literal Jan 2019 – Jan 2023 | San Francisco Bay Area B2B SaaS startup (Series Seed) enabling mobile app teams to visually analyze user flows — “Figma meets Mixpanel.” • Launched a multiplayer whiteboard with auto-generated, analytics-annotated user flows of screens. • Recruited top-tier engineering team; maintained high standards and strong culture. • Contributed heavily to product development, writing core frontend and video processing code (React, Fabric.js, Python, OpenCV, Rails, PostgreSQL). • Oversaw product, design, marketing, and investor relations as a multi-hat co-founder, balancing strategic direction with hands-on execution. • Wound down operations after not achieving product–market fit. ### Head of Data @ CareZone Jan 2017 – Jan 2018 | San Francisco, California Built data pipelines for marketing, business, and operations that enabled data-driven decision-making across the company (Looker and BigQuery). ### GM, Pharmacy @ CareZone Jan 2015 – Jan 2017 Operated and scaled high scale pharmacy business from launch to $6M ARR, ultimately serving 30K+ patients. Built front office and warehouse operations, ramping to 70+ FTEs in 4 months while ensuring compliance. Built HIPAA-compliant pharmacy CRM and workflow platform, including secure messaging to coordinate care and streamline operations. ### Head of Engineering, Product and Design @ CareZone Jan 2012 – Jan 2015 CareZone was a healthcare startup that made it easy for people to manage their medications, along with other health information. Our apps regularly ranked #1 in the Medical category, and served 4M+ users. Led the EPD org, shipping iOS/Android/web apps, continually running experiments. Reached product market fit with our patented medication scanning feature. Most importantly, we were fortunate to receive many, many glowing reviews about how we helped make our users’ lives a little bit simpler in the face of big healthcare challenges. ### VP Engineering @ Marvell Semiconductor Jan 2011 – Jan 2012 Led the global mobile software team (across Shanghai, Beijing, Hefei, Marlboro, and Santa Clara) that enabled customers to build mobile devices with Marvell chipsets by delivering performant, power-optimized Android software for application processor and single chip solutions, supporting TD-SCDMA and WCDMA. ### Director, System Software @ NVIDIA Jan 2007 – Jan 2011 Multiple leadership and management roles in the Mobile business unit, where we developed system software for Tegra ARM processor-based chips used in mobile devices (Microsoft ZuneHD media player, and Motorola’s Xoom tablet), automobiles (Tesla, Audi, BMW) and gaming devices (Nintendo Switch). Contributed to the first three generations of Tegra, managing various cross-functional teams responsible for chip and software bringup, continuous integration, build/release, SQA and diagnostics. Notably, drove the Tegra 2 bring up effort across teams in Santa Clara, Helsinki, Hyderabad and Pune to put first revision silicon in a form factor demo laptop browsing the web, running Flash. In true NVIDIA style, this effort took 11 days, working 24x7, after a year of preparation. ### Sr. Member, Consulting Staff @ Cadence Design Systems Jan 2006 – Jan 2007 Business and technical marketing role, working with sales engineers and account managers to go-to-market with a formal analysis tool called Incisive Formal Verifier that is used to verify the correctness of complex chip designs. Working with the West Coast sales account teams, we grew the regional business from $200K to $2.5MM through 30+ customer engagements, winning business from 15+ new customers. Distilled customer requirements into actionable feature enhancements by R&D, and interfaced with strategic customers to understand their verification methodologies and challenges, and identify where and how formal analysis and assertion-based verification could help them in their flows. ### Sr. Hardware Engineer @ Cisco Jan 2005 – Jan 2006 Senior member of the design verification team for a 100 Gb/s linecard ASIC in the CRS-3 core router. Also, member of Cisco’s cross-business unit ASIC Process Design Council working on standardizing design verification methodology and defect reporting. ### Sr. Member Technical Staff @ Vihana Jan 2003 – Jan 2005 Worked on the constrained random design verification infrastructure for a packet content inspection security ASIC. Verified software that programmed regexes in the ASIC. ### Staff ASIC Engineer @ Vivace Networks Jan 2000 – Jan 2002 Worked on a 20 Gb/s scheduler chip for the 320 Gb/s Tellabs Multiservice Router 8860 that was used for AT&T’s wireless backhaul. Design verification lead for a highly fault-tolerant and reliable switch fabric chipset supporting OC-192 ports and scaling to 2.5Tb/s. Defined the design verification methodology, developed the test bench and test plans, and drove chip bring-up. ### ASIC Engineer @ PMC-Sierra Jan 1998 – Jan 2000 ### Product Design Engineer @ Integrated Telecom Technology Jan 1996 – Jan 1998 ## Education ### Ph.D. in Information & Computer Science UC Irvine ### B.S. in EECS The Johns Hopkins University ### M.S. in CS The Johns Hopkins University ## Contact & Social - LinkedIn: https://linkedin.com/in/chikaichien --- Source: https://flows.cv/chikai JSON Resume: https://flows.cv/chikai/resume.json Last updated: 2026-04-05