New Analytical Placement engine to achieve runtime and QOR requirements for medium sized FPGAs

Standard cell validation tool development and support

Geometry operation tool support

Data Path placement

• Developed and supported relative placement tools for Data Path in

microprocessor designs using C++ and QT GUI.

• Created tool infrastructure, LEF/DEF Verilog parsers, relative placer

and graphical user interface to show placement results and to traverse

design hierarchy.

• Inserted clock buffers to drive flop rows such that the rest of the placed

design is less impacted.

• Cloned instances to reduce signal delay.

• Developed checkers for design rules.

Chip level net planning

• Generated more balanced blockage aware Steiner routes for chip level

nets planning in microprocessor designs. Buffers can be inserted on the

Steiner routes to meet skew and slew specifications.

CAD supported

• Supported designers to resolve issues when using ICC2, Conformal

formal verification tools and Virtuoso G-rule checker.

Floor planning & placement tools

• Developed next-generation floor planning tools to handle ASIC

design up to 4.5M cells on 32-bit machines with state-of-the-art

placer and ultra fast timer. The inputs are gate-level netlist, timing

constraints, and cell libraries. The outputs are detailed-router

friendly placed cells. From the benchmark results, fast timing

closure and shorter time to market are observed.

FPGA physical synthesis

• Created software infrastructure and develop algorithms for

FPGA physical synthesis. Optimized results by gate replication,

instance repacking/clustering, global route analysis, and

critical path analysis.