Firmware development. Working on ASIC bringup, NAND characterization, and performance optimization.

Designed 4KB LDPC solutions for PCIe Gen4 SSD controller (Tahoe), customized for Dell.

Developed advanced LDPC ECC algorithms with low latency and cost. Verified and validated in three ASIC generations: Shasta, Shasta+, and Tacoma.

Provided algorithms for many essential modules, such as random number generator.

Built up ECC software simulator and DPI functions from scratch.

Contributed the first low-power LDPC algorithm scheme for 2D and 3D NAND Flash, enabling reliability for top-tier product lines, including Client SSD (Gold S31 https://www.amazon.com/SK-hynix-Gold-NAND-Internal/dp/B07SNHB4RC) and Enterprise SSD (SE4011).

Developed LDPC-based ECC architecture on algorithm development and performance validation.

Led a team in development and evaluation of error-recovery algorithms on 2D/3D MLC/TLC NAND flash.

High-performance systems for the read channel of hard disk drives.

Invent a novel decoding algorithm achieving the highest hardware efficiency among up-to-date designs.

Develop a low-complexity LDPC decoder architecture for non-binary fields.

Build an effective non-binary error-correction mechanism for symbol-based turbo equalization.

Enhancements and analysis of the non-binary LDPC Decoding

Improve the decoder convergence by modifying the iterative scheme.

Develop a mechanism to mitigate the error floor, strengthening error-correction reliability.

Analyze the decoding behavior related to the codewords and trapping sets.