# Chung-Li W.

> Storage systems, algorithm research, firmware development.

Location: Fremont, California, United States
Profile: https://flows.cv/chungli

## Work Experience
### Staff Engineer @ Alibaba Group
Jan 2021 – Present | Sunnyvale, California, United States
Firmware development. Working on ASIC bringup, NAND characterization, and performance optimization.

### ECC Development Lead @ CNEX Labs, Inc.
Jan 2018 – Jan 2021 | San Jose, California
Designed 4KB LDPC solutions for PCIe Gen4 SSD controller (Tahoe), customized for Dell.

### Member Of Technical Staff @ Innogrit Corporation
Jan 2017 – Jan 2018 | San Jose, California
Developed advanced LDPC ECC algorithms with low latency and cost. Verified and validated in three ASIC generations: Shasta, Shasta+, and Tacoma.
Provided algorithms for many essential modules, such as random number generator.
Built up ECC software simulator and DPI functions from scratch.

### Senior Staff Engineer @ SK hynix memory solutions inc.
Jan 2013 – Jan 2017 | San Jose
Contributed the first low-power LDPC algorithm scheme for 2D and 3D NAND Flash, enabling reliability for top-tier product lines, including Client SSD (Gold S31 https://www.amazon.com/SK-hynix-Gold-NAND-Internal/dp/B07SNHB4RC) and Enterprise SSD (SE4011).
Developed LDPC-based ECC architecture on algorithm development and performance validation. 
Led a team in development and evaluation of error-recovery algorithms on 2D/3D MLC/TLC NAND flash.

### Staff ASIC Design Engineer @ LSI Corporation
Jan 2010 – Jan 2013 | Milpitas, CA
High-performance systems for the read channel of hard disk drives.
        Invent a novel decoding algorithm achieving the highest hardware efficiency among up-to-date designs.
        Develop a low-complexity LDPC decoder architecture for non-binary fields.
        Build an effective non-binary error-correction mechanism for symbol-based turbo equalization.

Enhancements and analysis of the non-binary LDPC Decoding
       Improve the decoder convergence by modifying the iterative scheme.
        Develop a mechanism to mitigate the error floor, strengthening error-correction reliability.
        Analyze the decoding behavior related to the codewords and trapping sets.

### Graduate Research Assistant @ UC Davis
Jan 2008 – Jan 2010 | Davis, CA
Construction of doubly-generalized LDPC Codes.
Constructed fast-encodable doubly-generalized LDPC codes.
Designed a min-sum based decoding algorithm.

Weight Distributions of LDPC Codes.
Analyzed multi-edge-type LDPC ensembles.
Studied asymptotic properties by using the optimization theory.

Development of doubly-generalized LDPC Codes.
Analyzed weight distribution and decoding thresholds.
Designed a min-sum based decoding algorithm with low complexity.


## Education
### Ph.D in Electrical and Computer Engineering
University of California, Davis

### Ph.D in Electrical Engineering
University of Hawaii at Manoa

### M.S in Communications Engineering
National Taiwan University

### B.S. in EE
National Tsing Hua University


## Contact & Social
- LinkedIn: https://linkedin.com/in/chung-li-w-65700119

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Source: https://flows.cv/chungli
JSON Resume: https://flows.cv/chungli/resume.json
Last updated: 2026-04-12