𝗡𝗔𝗦𝗔 𝗩𝗜𝗣𝗘𝗥 (𝗩𝗼𝗹𝗮𝘁𝗶𝗹𝗲𝘀 𝗜𝗻𝘃𝗲𝘀𝘁𝗶𝗴𝗮𝘁𝗶𝗻𝗴 𝗣𝗼𝗹𝗮𝗿 𝗘𝘅𝗽𝗹𝗼𝗿𝗮𝘁𝗶𝗼𝗻 𝗥𝗼𝘃𝗲𝗿)

• Implemented the Flash File System for NASA Ames’ VIPER. The file system uses Tuxera's Reliance File System over a FlashFX Translation Layer. The raw NAND flash module resides on a Broadreach DMOAB board and is accessible via the PCI backplane. The flash module uses Micron dies and the programming complies with ONFI (Open-NAND Flash Interface) protocol. The flash module provides hardware TMR and we added BCH EDAC. We optimized the file system for performance.

• Created a flash emulation layer that FlashFX can use. This emulation communicates over UDP (or TCP) to a host server which maintains a large bit file representing the flash media. This flash emulation is implemented under the Reliance+FlashFX and is included in our RAD750 emulation via QEMU.

• Development of the flash filesystem includes two flash geometries: the VIPER flight unit and the legacy LADEE development unit.

• Developed background tasks that trigger memory scrubbing of the flash disks. This task also triggers compactions when necessary. Adjusted the parameters of these tasks to achieve overall flash disk performance.

• Created a memory scrub cFS app that can send commands to the file system in order to report performance or usage stats or set flash disk scrubbing parameters. The app also reports file system EDACs as they occur.

• Implemented YAMCS ground system descriptions for file system commanding and telemetry points using XTCE.

• Developed bit error testing capability that can inject TMR errors during page reads or page writes.

𝗡𝗔𝗦𝗔 𝗕𝗶𝗼𝗦𝗲𝗻𝘁𝗶𝗻𝗲𝗹 𝗦𝗽𝗮𝗰𝗲𝗰𝗿𝗮𝗳𝘁 𝗙𝗹𝗶𝗴𝗵𝘁 𝗦𝗼𝗳𝘁𝘄𝗮𝗿𝗲

• Implemented EDAC (Error Detection and Correction) reporting for the NASA Ames’ BioSentinel satellite. The low-level VxWorks ISR gets called when the Reed-Solomon / BCH code doesn’t agree with its corresponding word in SDRAM / MRAM. The ISR scrubs the memory and packages a message which gets sent over the NASA Goddard cFS (core Flight System) bus which is then communicated to the ground system via telemetry.

• Constructed and tested the Flash Memory File System stack for NASA Ames’ BioSentinel satellite and includes WindRiver’s Highly Reliable File System (HRFS) over FlashFX Translation Layer over low level bit-banging GPIO code to affect page reads/writes and block erases. We also partitioned the 24 GiB raw NAND flash into three segments so that we could implement TMR (triple modal redundancy). A flash page is streamed in parallel to the three regions on the flash module. Also added EDAC with BCH codes for the case when TMR fails.

• Unlike our flight boards, our NEXYS 4 DDR dev boards do not have onboard flash. So I created a flash emulation layer that performs UDP to a host-side server that affects the page reads/writes and block erases to/from an 8 GiB file (no TMR). This is implemented in lieu of the GPIO code used on the flight unit.

• Developed background tasks that periodically scrub the flash disk memory.

• Created a memory scrub cFS app that can adjust flash file system parameters and report EDACs when they occur.

• Implemented ground software descriptions for the flash file system using NASA's ITOS (Integrated Test and Operations System).

• Implemented an in-flight VxWorks kernel patch facility that allows us to uplink a full VxWorks image patch. The patch uses binary file differences so that the uplink works with small patch files.

𝗠𝗼𝗱𝗲𝗹 𝗕𝗮𝘀𝗲𝗱 𝗦𝘆𝘀𝘁𝗲𝗺𝘀 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴 (𝗠𝗕𝗦𝗘) 𝗦𝗼𝗳𝘁𝘄𝗮𝗿𝗲 𝗗𝗲𝘃𝗲𝗹𝗼𝗽𝗺𝗲𝗻𝘁

• Wrote an XMI (XML Metadata Interchange) parser / generator in C++. This allows MEI to do data exchange between UML / SysML models in Rhapsody Systems Architect, Enterprise Architect or Papyrus and models in MATLAB / Simulink.

𝗠𝗶𝘀𝘀𝗶𝗹𝗲 𝗗𝗲𝗳𝗲𝗻𝘀𝗲 𝗔𝗴𝗲𝗻𝗰𝘆 𝗠𝗶𝘀𝘀𝗶𝗹𝗲 𝗦𝗶𝗺𝘂𝗹𝗮𝘁𝗶𝗼𝗻 𝗣𝗿𝗼𝗴𝗿𝗮𝗺

• Performed stability analysis for Sensor Sim, a multirate system composed of Simulink diagrams, S-functions, generated realtime scheduler and other Linux layers.

• Developed a rate monotonic scheduler for use on Concurrent’s iHawk multicore platform.

• Developed Simulink software to acquire and process images from a SMPTE board.

• Created a shared memory connection between Simulink tasks and a handwritten airborne processor.

• Investigated multicore real time performance in both the Sensor Sim and MDA missile simulation programs. Added performance logging capabilities.

• Created a block in Simulink to schedule subsystem code on separate threads (CPUs).

• Restructured an image processing algorithm to perform operations in parallel.

• Created a priority-based dynamic scheduling layer that keeps CPUs busy and alleviates the user from the labor-intensive load balancing exercises.

• Created an event chart that shows when tasks are computing, for how long and on which CPUs. It also shows the scheduling latencies, and which CPUs are idle and which ones are computing.

• Enhanced the dynamic scheduling algorithm to distribute its algorithm on multiple CPUs. This allowed for an order of magnitude more events per second to be scheduled. It also reduced the periodic jitter to acceptable values.

• Reworked the Xmath lexer/parser from using Lex/Yacc to using Flex/Bison.

• Refactored many C++ classes in Xmath to eliminate illegal mechanisms using template, functors and inheritance where appropriate.

• Restructured Xmath, a matrix math package, into a pure IPC server architecture.

• Defined a platform abstraction for MATRIXx using C++ classes and templates.

• Enhanced MATRIXx framework by creating the client interface to the Xmath server.

• Made external SystemBuild simulator libraries customizable from within the product. For this feature, the user annotates the model with code they want to call and we generate the makefile, invoke it creating DLLs (or shareable objects) and dynamically link the result back into the simulator.

• Created a user command player/recorder feature for VeriStand, an HIL (hardware in the loop) desktop tool.

• Developed new ODE/DAE solvers for the LabVIEW simulator. The solvers added were Adams-Moulton, Gear’s method for implicit systems, the SDIRK family, the Radau IIA family as well as DASSL. The solver coefficients were derived using Maple in quad precision as a future-proofing strategy.

• Implemented an event location mechanism for the continuous-time simulator. The algorithm works with a vector of nonlinear functions, is guaranteed to converge; has cubic convergence in the first three iterations; is superlinear thereafter.

• Developed ODE interpolants for each solver for use in the event root finder where the accuracy in the interpolation over the previous step uses information from the solver.

• Wrote compiler transformations which convert low level DSP blocks into LabVIEW diagram equivalents.

• Retargeted the OSEK RTOS kernel to the Mitsubishi M32R processor. The OSEK design provisions the kernel using static resources (tasks, queues, semaphores, etc).

• Implemented the protocol stack (IDB-C) for the automotive market. This effort implemented the link and transport layers of the ITS Data Bus (IDB) protocol. The physical layer was CAN. Thus the name IDB-C. This implementation was written to adhere to the SAE specification J2366/1.

• Led the release of Tornado 3.1 / VxWorksAE 1.1 for the Hitachi SuperH.