# David Garavaglia > Hardware ATE Test Engineer Location: San Jose, California, United States Profile: https://flows.cv/davidgaravaglia ATE Semiconductor Test engineer Over 20 years of test experience as a functional, semiconductor, and board test engineer specializing in ATE test development currently working a Synaptics designing test applications using LabVIEW and Python. Worked at Eagle Test Systems and Teradyne, designing test applications for power management, RFID, communication, power management , and boost/ buck regulators devices. Also worked as a trainer teaching engineers how to use Eagle Vision software and test equipment. Completed course work at UC Santa Cruz in SystemVerilog, semiconductor DFT. Currently taking classes in SystemVerilog Assertions and Xilinx FPGA programming. Completed LabVIEW Course I and II in 2017. - Expertise with all Eagle ATE test equipment including ETS 364, ETS 500, and ETS 600 Testers. - Developed Wafer Sort and Final Test Solutions using Eagle and Teradyne Catalyst ATE Test Equipment. - Designed load boards using OrCad schematic capture. - Developed TSU files for GSI M310 Laser Trimmers. - Proficient with oscilloscopes, voltmeters, RF generators , and other bench test equipment. - Developed I2C digital signal patterns for ATE equipment. - Wrote test patterns for INL, DNL, fuse trim, and binary searches. - Specify high frequency matching traces such as coplanar or microstrip. Specialties: Design turn key automated test solutions for power management, power regulators, RFID, communication, ADC's, and DAC's. ## Work Experience ### LabVIEW Software Engineer @ Intermolecular Jan 2020 – Present | San Jose, California, United States ### Electronic Engineering Test Technician @ Synaptics Incorporated Jan 2013 – Present | San Jose, California, United States Electronic Engineering Test Technician 03/2013 – Present • Developed LabView test applications to operate Rhode Schwartz Spectrum Analyzers, Agilent RF-frequency generators, and other USB and GPIB-controlled instruments using VISA and MAX. • Circuit design of test boards using current to voltage converters, 12 bit ADCs, FETS, voltage references. • Used Orcad schematic capture and performed DRC’s to check design layouts. • Parsed RF-spectrum data and performed statistical analysis, including variance, CPK, mean, and 3/6 sigma values, using MATLAB and C++. • Updated/executed bench-level/system-level tests on mixed signal ASICs, analyzed results searching for anomalies, experimental trends, and errors, and developed/published conclusions for review by senior engineering staff. • Designed electrical analog circuits using operational amplifiers and current to voltage converters and built prototype electronic circuits from hand drawn schematics. • Built, maintained, tested, and documented experiments and scripted/conducted data analysis. • Researched and selected vendors for board assembly and managed kitting functions. • Utilized various machine shop tools, including mills, laths, and numerically controlled high-speed routers. • Saved $20K in equipment costs by reverse engineering equipment operation, creating electrical schematics, writing operator’s manual, and repairing older thermal chamber equipment and high-pressure autoclaves. • Designed in-pressure safety switches to prevent operators from opening a pressurized chamber. • Designed-in pressure safety switches to prevent the operator from opening a pressurized chamber. • Created a client server application in Python/LabVIEW. The method was published and provide to staff engineers. • Streamlined lab workflow and saved on new part purchases by reengineering laboratory processes, sorting/labeling/ cataloging parts and equipment, and championing efficiencies in four electronic prototype labs. ### Electronic Engineer @ Dave's World of Test Jan 2009 – Jan 2013 Objective: ATE semiconductor Test engineer Over 20 years of test experience as a functional, semiconductor, and board test engineer specializing in ATE test development. Worked at Eagle Test Systems and Teradyne, designing test applications for power management, RFID, communication, power management , and boost/ buck regulators devices. Also worked as a trainer teaching engineers how to use Eagle Vision software and test equipment. Completed course work at UC Santa Cruz in SystemVerilog, semiconductor DFT. Currently taking classes in SystemVerilog Assertions and Xilinx FPGA programming. - Expertise with all Eagle ATE test equipment including ETS 364, ETS 500, and ETS 600 Testers. - Developed Wafer Sort and Final Test Solutions using Eagle and Teradyne Catalyst ATE Test Equipment. - Designed load boards using OrCad schematic capture. - Developed TSU files for GSI M310 Laser Trimmers. - Proficient with oscilloscopes, voltmeters, RF generators , and other bench test equipment. - Developed I2C digital signal patterns for ATE equipment. - Wrote test patterns for INL, DNL, fuse trim, and binary searches. Work Experience: Exar Cooperation 2008 – 2009 Senior Test Engineer Fremont, California Designed multisite ATE wafer sort and final test solutions for communication and power management and boost/buck regulator devices. Most challenging device was a 100 pin multiprotocol die with RS232 , V.35, V.10, V.11, and V. 28 capability. Worked on LED current controllers with I2C serial communication interface. Gave training classes on the use of the Eagle 500 and 364 testers. Was responsible for loading and maintaining Eagle Simulation software on the NT Computers. Developed guidelines for die sorting on the GSI M310 Laser trim equipment. Eagle Test Systems 2004 – 2007 Senior Test Engineer San Jose, California Teradyne 2001 - 2003 Senior Test Engineer San Jose, California ### Senior Test Engineer @ Exar Corporation Jan 2008 – Jan 2009 Designed multisite ATE wafer sort and final test solutions for communication and power management and boost/buck regulator devices. Most challenging device was a 100 pin multiprotocol die with RS232 , V.35, V.10, V.11, and V. 28 capability. Worked on LED current controllers with I2C serial communication interface. Gave training classes on the use of the Eagle 500 and 364 testers. Was responsible for loading and maintaining Eagle Simulation software on the NT Computers. Developed guidelines for die sorting on the GSI M310 Laser trim equipment. ### Senior Test Engineer @ Eagle Test Systems Jan 2004 – Jan 2007 Designed multisite hardware and software test solutions for power management semiconductors such as buck regulators, DACs, and RFID integrated circuits. Used OrCad, and Mentor Graphic PADs to lay out load boards. Gave two week training classes on Eagle Test Equipment. Average class size 10 engineers. ### Senior Test Engineer @ Teradyne Connection Systems Jan 2001 – Jan 2003 Designed ATE test applications for 8 bit 80MSPS ADC converters. These tests were for National’s ADC100 series of converters. Stripline and RF relays used for the analog outputs. A high speed 16 bit HSDU was used to measure AC signal outputs. Key measurements were taken such as SNR, full scale gain distortion, minimum sample and hold times, power supply distortions across voltage ranges. Also, INL was used test for gain and overall ramp distortion. DNL was used to test for missing of skipped steps at lower speeds. Most of the load boards were designed for dual or quad site testing. Separate ground plans used to prevent coupled site noise. The test was used to characterize the device over temperature, voltage, and frequency ranges. I also designed tests for power management and differential communication devices on the Catalyst and A510 testers. ### Senior Test Engineer @ Applied Automation Jan 1998 – Jan 2001 In charge of test development of gas chromatography instruments using LabView. Test development centered on National’s Instruments VXI card cage and instruments. ## Education ### BSEET in Digital Electronics and Analog Transistor Theory University of Silicon Valley ### BSEET in Electronic Engineering Cogswell Polytechnic College ## Contact & Social - LinkedIn: https://linkedin.com/in/sanjosedave - Portfolio: http://www.Synaptics.com --- Source: https://flows.cv/davidgaravaglia JSON Resume: https://flows.cv/davidgaravaglia/resume.json Last updated: 2026-04-10