# Dhrumeel Bakshi > AI Inference Systems Software Engineer at d-Matrix | ex-Google Location: San Francisco Bay Area, United States Profile: https://flows.cv/dhrumeel ## Work Experience ### Software Engineer, AI Inference Systems @ d-Matrix Jan 2025 – Present ### Software Engineer, Assistant Runtime Orchestration @ Google Jan 2020 – Jan 2024 | Mountain View, California • Assistant's core runtime platform responsible for multimodal conversation management, and for orchestrating various ML / NLP sub-services at query time. • Infrastructure to facilitate advanced conversational experiences via coordinating tightly coupled microservices. • Real-time delivery of speculative responses via bidirectional gRPC streaming. • Centralized serving components for user-state and context (persistence + retrieval), action execution, fulfiller selection etc. ### Software Engineer, Assistant Dialog Framework & Conversation Engine @ Google Jan 2017 – Jan 2020 | Mountain View, California, United States • Libraries and central infrastructure for dialog and user/session state-management, empowering dozens of teams developing Assistant features. • Engine to handle complex multi-intent dialogs, broadening semantic understanding and overall query recall. • Key components of the NLU platform, to enable the development of dialog-flows across multiple feature domains. • Developer tooling to improve debuggability and observability across all Assistant features. • Latency and capacity optimizations in the intent-to-fulfiller routing layer. ### Lead Member Of Technical Staff @ Mentor Graphics Jan 2015 – Jan 2017 | Fremont, California (Mentor Graphics was acquired by Siemens) R&D for the core backend of SLEC, leading formal equivalence-checking software for digital systems. • Specifically, the tool performs sequential equivalence checking of C/C++ spec against RTL (hardware model) which the output of HLS (high-level synthesis). • Implemented algorithms leveraging automated inductive reasoning to optimize, simulate and analyze operator-graph representations of users' designs. • The work involved dealing with the challenges of implementing scalable verification software, as well as brainstorming theoretical improvements to extract practical value from an equivalence-checker. ### Member of Technical Staff @ Calypto Design Systems Jan 2014 – Jan 2015 | San Francisco Bay Area (Calypto was acquired by Mentor Graphics) • Developed algorithms to optimize a compute-intensive software tool for formal property verification (5+ hr tasks). • Developed a sub-product to perform bounded-verification for intractable models. • Implemented heuristics and flows to orchestrate formal proofs via various backend constraint-solvers (bit-level, SAT/SMT, logic simulation). ### R&D Engineer @ Synopsys Jan 2012 – Jan 2014 | Sunnyvale, CA R&D for Synopsys' transistor-level static timing analysis tool (NanoTime). Owned and enhanced the logical reasoning module that improved analysis accuracy by providing inference on circuit graph-models. ### Graduate Researcher @ Virginia Tech Jan 2010 – Jan 2012 | Blacksburg, VA • Research on techniques for test-generation, encoding and compaction using SAT & SMT solvers and Linear Programming. • Worked on encoding deterministic tests for logic-BIST via LFSR reseeding. • Published research on algorithms to reduce on-chip storage for self-testing circuits. ### Graduate Technical Intern @ Intel Corporation Jan 2011 – Jan 2012 | Folsom, CA • Developed heuristics to improve FPGA based fault-emulation. • Developed algorithms and linear-programming formulations for test-compaction and test-time reduction ## Education ### Master of Science (MS) in Computer Engineering Virginia Tech ### Bachelor of Technology (B.Tech.) in Electronics Engineering National Institute of Technology Surat ## Contact & Social - LinkedIn: https://linkedin.com/in/dhrumeel --- Source: https://flows.cv/dhrumeel JSON Resume: https://flows.cv/dhrumeel/resume.json Last updated: 2026-04-11