Responsible for RF & digital circuit design, RF switching logic, matching circuits, interfaces, hardware/firmware integration, testing, certification for Wi-Fi chips used for DFS & Carrier Sense as part of a multi-receiver backhaul system in the unlicensed 5 GHz band

Project Management and Full development cycle experience for an RF system (including initial Schemetic design, Layout Design, Design review, First Article bring up, Production testing and support production with any issues)

Built and worked on numerous calibrated RF test setups for radiated and conducted measurements

Worked on several DFS and Carrier Sense projects for compliance with agencies such as FCC, ETSI, IC, and MIC

Worked on sensing and reducing enodeB emissions, prototype and bring up SFP, Dying Gasp, Carrier Aggregation,

Worked with FW team to define algorithm for DFS, Carrier Sense and Radio bootstrap

Worked on Qualcomm Atheros 9k and 10k codebase for Atheros Wi-Fi chips

Extensive Experience with various bus architectures such as SPI, PCIe, SGMII, HS-UART, I2C

Designed part of RF Front end PC Board for Rx only Wi-Fi chip, characterized DFS radar sensitivity at 5GHz

Worked on schematic, layout (Cadence Allegro) & integration of PCBs, supported production team in manufacturing & testing

Worked on Qualcomm Atheros 9k code base to program Wi-Fi chips

Worked on 1588 Module of frame based backhaul radio, wrote driver & module code to integrate QCA Wi-Fi chip

Created software to show graphical representation of device statistics