At Altera, I focus on implementing AI models for optimized FPGA deployment in various fields, including wireless communication and robotics. My role involves doin performance analysis and the development of custom hardware accelerators, ensuring efficient edge and PCIe-based platform implementations. I have experience in high-level design flows and deep learning applications. Overall extensively skilled and experienced in taking Algorithmic/Application specifications to FPGA Implementation targeting high performance acceleration.

Design of Hardware IPs for Digital Signal Processing(DSP), High Level Synthesis (HLS) Libraries for FPGA Implementation, Hardware Accelerators and HPC using FPGAs.

I worked as assistant professor in electrical engineering department of National University of Computer and Emerging Sciences Lahore. I taught courses like "Embedded System Design, Computer Aided Design of Digital Systems, Digital System Design, etc. " My research interest includes System Level Hardware/Software Design and modeling techniques, Hardware Design and RTL Architectures for Digital Signal Processing Systems, Video and Image processing,re-configurable hardware design, GPS/GNSS communication receiver etc.

Working with C-to-Silicon High Level Synthesis Tool R&D team. C-to-Silicon is a high level synthesis tool that can synthesize RTL description for hardware implementation starting from untimed C/C++ and SystemC.