# Edgardo Laber

> IC Design, Definition and Project Management (PMP®) – Mixed-Signal, Analog & Power

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/edgardo

Dynamic Analog and Mixed-Signal IC Design Engineering Leader with extensive experience driving innovative product development. Lead full integrated circuit product development process: product definition, technology aspects, circuit design and verification, tape-out, product evaluation and validation, and transfer to volume production. Expert in Battery Management ICs and mixed-signal product design, directing multi-site, diverse teams.

Builds and implements adaptive and disciplined methodology across automotive, power management, industrial, and consumer markets.  Crafts State-of-the-Art, High-Quality Products Leveraging Effective Collaboration.  Adept at engaging with customers for product definition, shaping automotive functional safety (ASIL D), and delivering complex solutions. Fosters environment of excellence, deep technical discussions, and respect. 

    • Project Management, PMP® Credential
    • Battery Management ICs (BMICs)
    • Battery Management Systems (BMS)
    • Customer Engagement
    • Automotive Functional Safety (ASIL D – FuSa – ISO 26262)
    • ESD / Latch-up / Hot-Plug Strategies
    • Foundry Process Selection
    • VerilogAMS and Device Modeling
    • Computer-Aided Engineering/Design (CAE / CAD)
    • Analog & Mixed-Signal Circuit Design
    • Standard Implementation
    • Patents and Intellectual Property
    • IEEE Senior Member
    • Continuous education: IEEE ISSCC, MEAD, CU, ISO 26262
    • Cadence analog and mixed signal design tools
    • US Citizen
    • 13 US patents (BMS, non-volatile memory, and chip interface)

## Work Experience
### Principal Design Engineer @ Alpha & Omega Semiconductor
Jan 2025 – Present | Sunnyvale, California, United States

### Advisor - Analog IC Design @ Ai Linear
Jan 2025 – Present

### IC Definition, Design and Project Management Consultant - Mixed-Signal, Analog, and Power Management @ Unknown
Jan 2024 – Jan 2025 | United States

### Sr. Manager, Design Engineering, Automotive Business Unit @ Renesas Electronics Corporation
Jan 2017 – Jan 2024 | Silicon Valley, California, United States
Automotive, Power Management, Industrial & Communications, Computing and Consumer Products

    • Instituted and expanded the original BMIC design team, spinning-off, guiding and supporting additional design teams.
    • Supervised the more difficult and key BMIC products with small and large design, verification and layout teams, personally innovating critical blocks.
        - These products operate up to 120 V, integrating robust hot-plug capability for connecting to series battery cells, incorporating cell balancing, redundant monitoring, and precise cell voltage measurements, along with daisy chain communications and automotive functional safety features (FuSa – ISO 26262).
        - Engineered BMICs for power tools, UPS systems, e-bikes, and home appliances, delivering optimized power management solutions tailored to each application.
        - Products include: ISL9208/16/17, ISL94208, ISL78600/601/610, ISL78700/714, ISL94203, ISL94212, ISL94216, RAA271700, RAA271716/14/12/20/22, RAA489210

    • Oversaw product development and designed individual blocks for wide variety of power management products.
        - Created voltage regulators, including low and high power LDOs, MOSFET drivers, bridge drivers, ORing FET controllers, buck-boost USB-C chargers, buck converters with and without integrated FETs and drivers, DC-DC auto/industrial controllers, multi-phase computing PMICs and controllers, capacitor dividers, and poly fuses.
        - Products include: ISL90840/1/2/3, ISL96016, ISL88163, ISL89367, ISL89160/1/2/3, ISL80101/101A/121, ISL80103, ISL6146, HIP2103, HIP2104, ISL78302, ISL8505, ISL78229, ISL95905, ISL95530, ISL95855/57/59/28/29, ISL95865, RRB96800

### Sr. Design Manager @ Intersil (acquired by Renesas)
Jan 2004 – Jan 2017
See details above, under Renesas description.

### Design Manager @ Xicor
Jan 2000 – Jan 2004
Programmable Mixed-Signal Products with Embedded High Reliability EEPROM

    • Collaborated with Applications and Product Marketing Engineers to define chips tailored for sensor and optical transmitter control, optimizing performance and flexibility in the overall system.
    • Devised key analog circuits and aligned overall design teams, ensuring cohesive project outcomes.
        - Implemented various functions, including EEPROM cells and analog support circuits, digitally controlled potentiometers (DCPs), laser diode driver bias, sensor bias, charge pumps, DACs, ADCs, CPU supervisors, and low-power circuits (crystal oscillators, various other oscillators, references, comparators, amplifiers).
        - Products: X9530, X96010/1/2, X79000/1/2, X95840

### Design Manager @ Micro Linear
Jan 1993 – Jan 2000
Networking Physical Layer Products

    • Spearheaded definition, design, and management of Ethernet / Fast Ethernet and Token Ring physical layer (PHY) transceivers and media converters (twisted pair, coax, and fiber optic) using BiCMOS technologies.
    • Played key role in shaping TIA/EIA-785 Standard for 10/100 MB/s Auto-Negotiation on Fiber Optic and Media Conversion, establishing standards in silicon and actively participated in IEEE 802.3 and 802.5 committees.
        - Built critical circuits within PHYs, including MII digital interface, PLL, twisted pair transmitter, fiber optic LED driver and quantizer, scrambler and descrambler, serializer and deserializer, and auto-negotiation functionality.
        - Products: ML6651, ML6652, ML6680, ML6682, ML6686, ML6691, ML6692/4/5/6/7/8.


## Education
### Master of Science in Electrical Engineering
San José State University

### Ingeniero Electrónico in Electrical and Electronics Engineering
University of Buenos Aires

### Colegio Nacional de Buenos Aires


## Contact & Social
- LinkedIn: https://linkedin.com/in/edgardolaber

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Source: https://flows.cv/edgardo
JSON Resume: https://flows.cv/edgardo/resume.json
Last updated: 2026-04-13