# Eric Gayles, Ph.D. > Senior Engineering Director, Advanced Research and Development Location: Cupertino, California, United States Profile: https://flows.cv/ericgaylesphd Award-winning Engineering Design Manager with 18+ years senior-level experience: Microprocessor design management, Machine Learning, Mobile, Engineering Lead, Advanced Research PM, Google, Director with Intel Research, Senior Research Analyst, and VC consultant. Spearheaded the productization of 10+ complex E2E IC technologies in High Performance Microprocessors, ASICs, SOCs, Cell Phones, Mixed-Signal Designs and Platform solutions; 6 U.S. Patents, 10+ Papers Led/inspired teams on projects of up to 500 in the USA/Latin America/Asia TECHNOLOGIST & ENGINEERING MANAGEMENT: Systems • Processors • Software • IP * Database, Cloud and Big Data Analytics * Hardware architecture and platform development * Software Product management * Machine Learning HIGH PERFORMANCE CPUs: Advanced Circuit Design • Mixed Signal • I/Os • HVM • Process Migration • EDA * 10+ Tapeouts of performance-leading products in high volume E2E deployment * Google's Tensor Flow ASICs * 1st PCH (Next gen Southbridge) for CPU+Graphics integration * Intel’s 1st High Speed, 4-Way FSB architecture for servers and Intel's 1st C4 IA processor LOW POWER ELECTRONICS: ASIC Development • Computer Arith. • Environmentally Sensitive Design • Low Power Embedded Systems • Low Power Synthesis * Circuit innovations & BKMs that lower power consumption 30% across CPU designs * CAD suite predicting chip power per application to within 3% of actual * Power-reducing strategies, modeling & product spec ownership which drove several growth market design wins across 3 product generations SOC & CONNECTED COMPUTING: Advanced Memory Architectures • CBD/ Synthesis • HIP/SIP Mgmt. * Intel’s first IA Core for SOC – Digital Home and IoT * Platform delivery (HW/SW/Firmware) for 2 generations of Connecting Computing Platforms * DSP Architectures * Next Gen. Memory & Storage Architectures driving $1B in BOM savings/30% in projected power reduction over the next decade ## Work Experience ### Senior Principal/Director AI/ML SOCs & Chiplets - Delivering world class, scalable AI Performance @ Tenstorrent Jan 2024 – Present | Santa Clara, California, United States Leading technical planning, program management, and execution for our AI/ML silicon IP and chiplet development. Tenstorrent is building the future of AI compute — combining RISC-V CPUs, scalable chiplets, and open-source innovation — and I’m excited to help accelerate that vision. Over the past year, I’ve been privileged to provide leadership across our next-generation AI SoC — the most configurable, high-performance inference ML engine in the industry, supporting all contemporary models. Established an execution cadence and design management that aligns our engineering teams with our manufacturing partners and customers. ### Silicon Development and Technical Management @ Google Jan 2015 – Jan 2024 Leading technical development and enabling of key feature innovation across several of Google's industry-leading products including Google Platforms, Machine Learning accelerators, YouTube, and Pixel. ► Google's Machine Learning ASICs - Tensor Processor Unit (TPU), Pixel Cellphone. Specifically led engineering activities within Google's Tensor Processor team. This included EDA tools, management of our flexible workforce and external development partners, and design methodologies. ► Managed development and system integration of Machine Learning ASIC in the Pixel Cellphone. ► YouTube compute and data infrastructure. Led software development and prototyping for a new resource management application covering Cloud, Compute, Storage, Networking, and Accelerators. ► Software development - Android for Pixel, Machine Learning feature sets covering audio pipelines and gesture recognition. ### (Concurrent) Lecturer - Digital Systems, Machine Learning (Grad Level) @ University of California, San Diego Jan 2015 – Jan 2018 Classes taught across the UC and Cal State System include: ► Digital System Design - Covering Computer Organization, Transistor Operation, VLSI, Verilog, Arithmetic Circuit Block Design. ► Machine Learning (Grad Level) - Topics include Supervised and Unsupervised Learning, Probabilistic Classification, ML-based Regression techniques, HMMS, Convolutional and Recurrent Neural Networks, and Deep Learning. ► Information Systems and Strategy (Grad Level) - Managing information to create business value. Planning, organizing, and leading information systems initiatives. Relationship of data, information, and knowledge to strategic and operational decision-making. Global aspects and ethical uses of information systems. ### Executive Platform Development Manager and Design Lead for Enterprise Data Center Solutions @ Teradata Jan 2013 – Jan 2016 Teradata is an industry leader in advanced high-performance database design, analytic data platforms, data insights-driven marketing applications, and data warehouse solutions. Teradata’s Hardware Platforms, Database solutions, Machine Learning, and Advanced analytics products cover Big Data, Enterprise Data Warehousing, and Cloud. ► Led engineering and development for the Enterprise Platform product line. Enterprise Platform solutions and their related products represent over $1 Billion in annual revenue for Teradata. Delivered platforms (Project Management / Program Management) covering three generations of industry-leading high-performance data analytics technology. The EDW offering is built on a Massively Parallel Processing (MPP) architecture. ► Led the engineering development, prototyping, manufacturing, and full deployment for Teradata's first all-SDD and first DDR4-based platforms. ► Deployed innovations including improvements in Hot Storage, Memory, and Compression technologies. ### Technical Director and Solutions Architect with Intrinsix / Senior Adjunct Research Member for IDA @ Institute for Defense Analyses Jan 2012 – Jan 2015 | Washington, District of Columbia, United States ► IDA (Institute for Defense Analyses) – operates three Federally Funded Research and Development Centers (FFRDCs) in the public interest: the Systems and Analyses Center, the Science and Technology Policy Institute, and the Center for Communications and Computing. ► IDA brings the best scientific, technical, and analytic talent to bear on strategic issues critical to U.S. National security. Concurrently, served as Technical Director and Solutions Architect with Intrinsix. Operating from Silicon Valley Eric partnered with Intrinsix's industry-leading clients to understand customer requirements and engage development efforts. He worked together with clients to architect and provide technical leadership for their Mixed-Signal ASIC and SOC solutions. ► Provided technical leadership on customer projects. ► Technology development in analyzing customer requirements, architecting and proposing solutions. ► Crafted state-of-the-art solutions for complex Mixed-Signal design problems. ► Managed ASIC and SOC engineering design resources. Intrinsix is the leading independent electronic design services company, providing product development outsourcing to the world's leading electronic systems companies. Its distributed and global presence drives customer time-to-market requirements via unparalleled capabilities and local support. ### Engineering Director / Senior Technical Strategist @ Intel Corporation Jan 2008 – Jan 2012 | Santa Clara, CA ► Maintained complete oversight and delivery of a prototype for Intel’s successful program focused on advanced memory/storage hierarchies and next-generation SOC strategies; defined a new architecture to support coupling of Intel architecture and NVM for innovations in ultra-thin notebook and tablet platforms. ► Led/developed Intel’s management of the Open Cirrus cloud computing global consortium with $30M in total funding for high-performance cloud computing platforms and effective design methods to increase performance. ► Managed Intel’s global effort for University Research partnerships to promote product advancements in High-Performance Graphics, Embedded Architectures, Semiconductor Manufacturing, Parallel Computing, and Wireless Healthcare. ### Engineering Manager / Program Manager / Product Manager – CPU, SOC, Digital Home @ Intel Corporation Jan 2004 – Jan 2008 | Santa Clara, CA ► Managed several of Intel’s high-impact transformative Consumer Electronic processor programs and manufacturing for 4 years. ► Responsible for the development of 5+ new products impacting teams of 100-500 designers at 6 global sites in the USA (California/Arizona), the Middle East (Israel), and Asia (Malaysia). ► Productivized all on schedule earning the company billions of $ in revenue and setting the basis for several generations of future products on multiple roadmaps. ► Productized Intel’s 1st IA SOC and 1st PCH processor. ### Circuits Design Manager / Low Power Research Manager – Intel Architecture Group @ Intel Corporation Jan 1996 – Jan 2004 | Santa Clara, CA ► IA Core Digital Cluster development, Analog Design and Design Automation, and supervising teams of 10-25 Circuit Design Engineers, Mask Designers, and Design Automation Engineers. ► Managed the Circuits Lab – Low Power Research Group: Assessed the company’s state of the art and successfully developed/deployed new circuit techniques across various projects, targeting the highest ROI opportunities. ► Served as a Senior Manager on a significant number of Intel Microprocessor products directing high-value, advanced strategic research initiatives. ## Education ### Ph.D. in Computer Science & Engineering in Computer Science and Engineering Penn State University ### B.Sc. in Computer Science in Hons. University of Maryland Baltimore County ## Contact & Social - LinkedIn: https://linkedin.com/in/ericgayles --- Source: https://flows.cv/ericgaylesphd JSON Resume: https://flows.cv/ericgaylesphd/resume.json Last updated: 2026-04-05