# Eric Yu >  Senior Reliability Engineer at Apple, ASQ CRE Location: San Francisco Bay Area, United States Profile: https://flows.cv/ericyu 9 years of experience in the display and consumer electronics industries: 5 years in display module and product reliability and failure analysis, 4 years in IGZO TFT process integration. ASQ Certified Reliability Engineer. Experienced in working with and Asia-Pacific suppliers and contract manufacturers from from NPI through mass production. Native speaker of English and Mandarin Chinese, with advanced proficiency in Japanese (Japanese Language Proficiency Test 日本語能力試験 N1, certified December 2018). Citizenship: Taiwan, New Zealand Work Authorization: US Permanent Resident (Green Card) ## Work Experience ### Senior Reliability Engineer, Product Operations @ Apple Jan 2020 – Present | Cupertino, California, United States - iPhone 16 Plus: iPhone system reliability, FACA, ORT - iPad Pro 11"/13" (2024): display module reliability, FACA, ORT - iPad Pro 12.9" (2021, 2022): display module and Mini-LED BLU reliability, FACA, ORT - Macbook Pro 14"/16" (2021, 2022, 2023): Mini-LED BLU reliability, FACA, ORT - Apple Watch Ultra (2022): display module ORT readiness - iPad Air 5 (2022): display module reliability, FACA, ORT - iPad Mini 6 (2021): display module reliability, FACA, ORT - Apple Vision Pro (2024): display module reliability and FACA ### Senior Reliability Engineer @ OmniVision Technologies, Inc. Jan 2019 – Jan 2020 | San Francisco Bay Area • Coordinated LCOS display reliability qualification projects with cross-functional teams for new product introduction and process/material/site changes • Performed failure analysis of LCOS displays for product qualification and customer complaint resolution, leading to corrective actions and lessons-learned • Developed product-level reliability specifications for LCOS products based on customer mission profile, risk assessment, and industry standards (JEDEC JESD22) ### TFT Device Engineer @ Royole Corporation Jan 2015 – Jan 2019 | San Francisco Bay Area • Developed TFT active matrix backplane technology for flexible AMOLED displays through DOE, device and material characterization, and failure analysis. • Characterized TFT electrical properties (I-V, C-V, bias-temperature stress) and presented analytical findings to stakeholders within the US and Chinese R&D teams for critical technology development items, e.g. TFT structures, thin film stack, and evaluation of outside supplier materials/technologies • Defined and optimized the US R&D lab baseline process parameters for various TFT structures • Managed US R&D electrical test lab, duties include: evaluation of test equipment for purchase, interfacing with equipment vendors as the primary technical contact window, and mentoring of junior test engineer • Collaborated with Chinese R&D team on the transfer of TFT process integration insights and measurement best practices through web conferencing, on-site visits, and in-person seminars • Designed TFT parameter extraction internal web app in Python/Django, with 10–20 active users between US and Chinese R&D teams ### TFT Process Engineering Intern @ Qualcomm Jan 2011 – Jan 2011 | Greater San Diego Area • Fabricated and optimized high-performance amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) by photolithography for Qualcomm Mirasol reflective display prototype • Optimized TFT fabrication process and a-IGZO sputtering conditions using shadow-mask ## Education ### Ph.D. in Electrical Engineering University of Michigan Jan 2009 – Jan 2015 ### M.Eng. in Electrical and Computer Engineering Cornell University Jan 2008 – Jan 2009 ### B.Sc. in Electrical and Computer Engineering Cornell University Jan 2004 – Jan 2008 ## Contact & Social - LinkedIn: https://linkedin.com/in/erickyu --- Source: https://flows.cv/ericyu JSON Resume: https://flows.cv/ericyu/resume.json Last updated: 2026-03-23