# Frank L.

> Sr ASIC III engineer at Amazon Lab126

Location: Santa Clara, California, United States
Profile: https://flows.cv/frankl1

## Work Experience
### Sr ASIC III design engineer @ Amazon Lab126 Developmet
Jan 2013 – Present
Play key roles in design and integration of SoC projects and release the netlist to the back-end vendor for PnR. Design ISP blocks and integrate others for image nodes. Evaluate vendors to provide IP for design. Review vendor designs, propose solutions for integration, and collaborate with vendors to ensure integration with ISP. Leverage tools to check code along with synthesis tools to check timing and power.

Highlights
•	Worked with the vendor to architect communication interface of MIPI DPHY and CSI2 controller with SOC.
•	Set up the vendor’s MIPI Verilog code to Amazon Lab’s verification environment for design verification (DV).
•	Set up RTL design guidelines for projects.
•	Completed RTL design ISP and worked with DV to verify the block against the model.

Design Projects
•	RTL design camera front-end ISP block, including block-level correction, defective pixel correction, and geometry distortion correction and pixel histogram calculation
•	Block diagram of audio beanforming and filter design
•	Architecture implementation of convolution neural network (CNN) machine learning Alexnet, Google net, VGG net forward path

Integration Projects
•	MIPI CSI2 Rx/Tx controller and DPHY IP to SoC include APB register map decode, ISP interface, signals synchronization, DFT implementation
•	MIP core to ISP streaming interface
•	MIPI DSI2 Rx/Tx controller and DPHY including command mode to timing controller SoC chip for Liquavista EWD video display
•	Synopsys’s Ethernet IP for 10GBase-KR including XGMAC, PCS layer, and E12GPHY to SoC using coreConsultant for configuration
•	Cadence’s Tencilica HIFI 4 Audio DSP processor with microphone input

### Principal Design Engineer @ Netlist, Inc
Jan 2010 – Jan 2013
Defined u-architecture specification of chipset rank multiplication for HCDIMM and SM and SPI bus register control for software download. Modified DDR3 model for DDR4, host, IO, and DLL/PLL for simulation. Developed RTL design in Verilog for RCD01/DB01 chipsets, including power-down mode. Performed SM and SPI bus interface RTL design, including debug and programmable scheme. Verified the chipsets in DIMM subsystems leveraging Verilog, Perl, and Tcl script. Conducted synthesis using DC and RC for timing closure and sign off. Collaborated on testing and debugging.

Highlights
•	Delivered a DDR4 DB01 design and RCD01 design for a new JEDEC definition and specification.
•	Worked with the vendor to get the IP defined and meet DIMM specification.


Projects
•	DDR3 32GB RCD design for HCDIMM, including RTL design synthesis and timing closure
•	Collaboration with the test engineer to characterize and bring the DDR3 RCD and DB chip to volume production
•	Generation of PIC code for system bring-up and debug the performance of DDR timing

### Principal Design Engineer @ Bay Microsystems
Jan 2000 – Jan 2010
Managed the entire ASIC design flow, including u-architecture definition, RTL design verification, synthesis and timing closure, device bring up, and ATE testing on numerous projects.

Highlights
•	Delivered an advanced high-speed networking interface chip, including SPI5, SFI5 interface, and network processor egress design.
•	Successfully met the challenge of providing numerous safeguards for complex specifications to maintain signal integrity of the design, and collaborated with software developers on protected functions.

Projects
•	TM (traffic management) on Altera FPGA for 40G systems using Altera Quartus Tools from u-architecture to FPGA RTL implementation
•	40G/4x10G SerDes framer interface level 5 (SFI5) PHY design on high-speed 40G SONET/OTN framer chip working from OIF specification, architecture, and u-architecture, defined control register, RTL design to chip bring-up testing
•	40G/4x10G system packet interface level 5 (SPI5) PHY design on high-speed 40G network processor (NPU) chip from OIF specification, architecture, and u-architecture, defined control register, RTL design to chip bring-up testing
•	Egress queue/trunk/segment-level packet editing, alignment, packet padding and multicast design on high-speed 40G NPU chip working from u-architecture, RTL design to chip bring-up testing
•	SPI4.2 and SPI4.1 interface verification on 10G classification chip
•	SPI3 interface design for OC48 TM NPU chip from OIF specification, u-architecture, RTL design to chip testing
•	Egress ATM, Internet packet, and CSIX multicast design for 10G NPU chip working from u-architecture, RTL design to chip testing

### VLSI design manager @ C-Cube microsystems
Jan 1990 – Jan 2000
Take responsibility to lead the team from definition, micro-architecture, 
rtl design, verification, synthesis, place/route, timing closure and tape out
chip on numerous  projects.
            1. SOC MPEG II DVD decoder
            2. Audio/Video MPEG II Decoder for DVD, PC and set-top box (STB).
            3. MPEG II Set Top Box decoder chip join design with JVC.
            4. Work with vendor to build first MCM chip for Encoder systems to run
                AFF application microcode. 
            5. MPEG II encoder chip. 
            6. Design Motion Estimation for MPEG I encoder project, write
                C model, logic and circuit design, layout, ATE testing, chip debug.
                Burn-in, transfer to production

### Design MTS @ AMD
Jan 1988 – Jan 1990
Responsible for design for 29K co-processor and memory controller projects 
logic design and circuit design, optimization, timing check and check layout.


## Education
### MSEE in Computer Engineering
The University of Texas at Austin


## Contact & Social
- LinkedIn: https://linkedin.com/in/frank-l-79baa221

---
Source: https://flows.cv/frankl1
JSON Resume: https://flows.cv/frankl1/resume.json
Last updated: 2026-04-13