* In charge of the company's development of high-speed, high-performance CMOS analog / mixed signal IP design for the cutting edge optical transmission systems, including but not limited to ADC, DAC, low-jitter PLL, etc. in TSMC 5 nm and 3 nm technology nodes.

* In charge of the company's development of the low-power, low-noise, high-resolution photonic IC (PIC) controller.

* Have built the team from ground up; Currently managing and supervising ~30 people at multiple sites accross the globe.

* Guide the team to valuate CAD tools and constructe the efficient design environment.

* Establish the design methodology and layout guidelines to help the team to be more efficient and effective. Direct the team to apply the right process to minimize the overhead.

* Provide technical guidance to the team; groom and equip the team with the latest design knowledge.

* Help the company define the business strategy in terms of IP development priorities.

> Leading the development of low-power high resolution analog IPs, including but not limited to ADC, DAC, regulators, oscillators, touch controllers.

> In charge of the analog IP development of the flagship MCU flagship products, including but not limited to C21, aiming for industrial and automotive applicators, and L21, aiming for low-power IoT applications.

Currently I have 10+ direct reports local and remote under my supervision. Also, there are 10+ engineers technically supervised by me. I am leading a mixed signal design / layout team engaging in the implementation of the PMA layer of ultra-high-speed (10 Gb/s+) multi-standard serial links with TSMC's advance processes.

In charge of:

* Low-Power UniPHY (multi-standard, multi-rate) for rates from 1 Gb/s to 12.5 Gb/s;

* Burst-Mode Transceiver.

Technical capabilities:

* CMOS Transmitters, PLL/DLL, Receiver Front-End, Clock and Data Recovery.