Experienced Software Engineer with a demonstrated history of ATE test program development in the semiconductor industry. Interested in software development and skilled in C, C++, Python, and Lua. A technical leader with a strong focus on quality and discipline.
Experience
2021 — Now
San Francisco, CA
Led WRAP Phase 3 (Worldwide Regional Awareness Program) technical standardization affecting 50+
engineering teams, creating common design patterns and leading twice-weekly working groups, delivering
$240M+ business value through merchant identifier migration
Architected cloud services integrating UKG Pro Workforce Management with Amazon’s HR systems and
frontend apps, building Lambda-backed API Gateway service with Step Functions and DynamoDB persistence
enabling shift scheduling for 10,000+ associates across 87 stores with $1.5M annual cost savings
Orchestrated zero-downtime migration from DUB to ZAZ regions, managing an overseas contract engineering
team to implement cross-region replication and comprehensive integration testing across 5+ backend services
for SVP-priority infrastructure initiative
Championed AI-native development practices by evaluating and promoting Amazon Q, Kiro CLI, and MCP
servers; established best practices documentation and built production automations reducing development time
by 10+ hours/developer/week
Engineered Labor Scheduling Knowledge Base using Amazon Kendra with automated Git-to-S3 sync pipeline
enabling AI access to search-indexed OpenAPI specs, source code, and 430+ internal documents, supporting
faster agentic development and improved developer onboarding
Designed flexible barcode scanning system for grocery fulfillment, dynamically determining scanning
requirements based on product category hierarchies, reducing unnecessary scans by 25% and improving
associate productivity by 12% across 500+ stores
San Francisco Bay Area
Leading a code re-architecting team that has reduced code complexity by 55% in one quarter as measured by nested statement depth, file lines, function lengths, and modularity score.
Managed an AGILE development team of 5 engineers through two program lifecycles through requirements gathering, roadmapping, developing, testing, and on-time manufacturing release.
Presented software development techniques and tools to my organization of 250+ engineers. Then helped teams improve their development processes, including adopting a pull request workflow and switching to a monorepo, reducing code duplication by 98%.
Designed Jira workflows for development and tracking that allow for automated status tracking via REST API and PowerBI dashboard.
Reduced GNU Make build time by 95% by implementing a new serialization library, enabling faster development and automated builds.
Implemented QuickBuild continuous integration for automated build checks and nightly regression test suite of a repository that has reduced program defect severity by 60% through early detection.
Santa Clara, California, United States
Improved test algorithms that increased silicon yield by 40% and reduced test time by 50% while maintaining quality as measured by defect rate and device I/O performance of over samples of 10,000+ units.
Translated mature Python-based program to C with support for new hardware and new vendor libraries and demonstrated equivalent device performance and test coverage through correlation with 10,000+ units.
Burlington, Vermont Area
Built a Verilog test suite to verify an SRAM ASIC design simulation performs to datasheet specification.
Identified and worked with designers to correct crucial design bugs such as inverted logic and incorrect signal connections preventing million dollar post-silicon fixes and significant delays.
Performed stress-test simulations of pre-silicon design to confirm ASICs meets lifetime reliability expectations.
Education
2012 — 2015
Penn State University
Bachelor of Science - BS
2012 — 2015