Verification of fabric and configuration in leading-edge SoC FPGAs.

Verification of fabric and configuration in leading-edge SoC FPGAs.

Verification of configuration subsystem in 20nm Arria 10 FPGA. Tasks included verification of control block logic supporting on-chip micro-controller using UVM, development of parametrized models for configurable memory (CRAM) and embedded memory (ERAM), and verification of full chip configuration of CRAM and ERAM. Identified and closed 100+ bugs.

Design and verification of embedded memory in 28nm Stratix V FPGA. Tasks included architecture evaluation and implementation, RTL model coding, Logic Equivalence Check between RTL model and schematics, programmable clock path optimization, and logic verification using Verilog. Simplified design effort by consolidating 2 types of embedded memory (144K and 9K blocks in 40nm) into 1 single 20K block while meeting customer requirements. Competitive study showed Stratix V embedded memory achieved better performance with a smaller area when compared to the major competition (700MHz vs 600MHz from published data sheets).

Design and verification of embedded memory in 65nm Cyclone III FPGA. Tasks included new feature definition, floor planning, data path optimization, logic verification using Verilog, performance and Vccmin simulation using HSIM, timing model generation and scan chain timing closure using Nanotime.

Design and verification of embedded memory block in 90nm Hardcopy II structured ASIC. Tasks included developing RTL model for memory array, block level logic verification and timing model generation.

Full-chip netlist generation for ECP FPGA. Tasks included development of PERL scripts to generate full-chip Verilog and CDL netlists, which were used in logic simulation and LVS respectively, development of Verilog behavior models to speed up logic simulation, providing support to debug full chip logic simulation failures and full chip LVS errors.

Gate-level circuit design for bandgap references, SRAM read/write circuits, ripple-carry adder and power-on-reset circuits in Mach CPLD. Tasks included design verification and performance optimization using HSPICE.