# Hrant Muradyan > Sr Architect Product Applications Engineer at Synopsys Inc Location: Santa Clara, California, United States Profile: https://flows.cv/hrant 20 years experience in EDA software testing and customers support. Good understanding of Custom IC flow, physical verification, PDK development and OA database infrastructure 5 years extensive experience in PLD, FPGA and mixed-signal VLSI design with progressive increase of responsibilities and management of team. High proficiency in Verilog HDL. Additional extensive experience in Spice, TCL, Perl, Python, PHP, Matlab package. ## Work Experience ### Sr Architect Applications Engineering @ Synopsys Inc Jan 2020 – Present | San Francisco Bay Area ### Senior Manager, Custom Design @ Synopsys Inc Jan 2016 – Jan 2020 | San Francisco Bay Area ### Staff Corporate Applications Engineer/Manager, Custom Design @ Synopsys Inc Jan 2010 – Jan 2016 | Mountain View, CA Customer support Lead training Migrate legacy designs Develop custom flows, utilities Develop HSPICE, CDL and Verilog netlisters Discuss new features with customers, define and provide requirements for R&D New features prototyping on Tcl Reviewing product specifications. Managing a team of Corporate Application Engineers working on the Synopsys' Custom Design products ### Corporate Application Engineering Manager, Custom Design @ Synopsys Inc Jan 2005 – Jan 2010 Coordinate 5 person team works During 2007 also performed responsibilities QA department manager Give tasks to team members and check the quality of their work Work with customers: provide custom solutions, develop design flow Prepare training materials and demo designs for customers Testcases development/review Send reports to high level managers ### Lecturer @ State University of Armenia Jan 2006 – Jan 2009 Conducted lectures and practical courses for BS and MS students in department of Applied Mathematics Digital Circuits Introduction to VLSI Design Basic electronics circuits Verilog HDL ### IC design engineer @ Epygi Technologies Jan 2000 – Jan 2005 Started as engineer responsible for development and verification of specific DSP functions: CRC, Scrambler, Error Correction Code (Reed-Solomon encoder/decoder) on Altera FPGA family using Verilog HDL. During the 2 last years coordinating a 6-person team in complex projects, responsible for design, prototype, and test bench, layout and debug mixed-signal IC. Development of PCBs for testing hardware prototypes elaborated by the team. Providing training courses on Verilog HDL for the company employees. Key Projects: Functional and timing verification of CPLD design developed by HW group for Legerity Corporation. PCI2HPI. Design bridge on Altera PLD between MPC8280 PCI bus and 8 bit HPI ports of several TMS320VC5502 DSPs (at least 4). Created guideline with recommendations for HDL coding and prototyping the core of FPGA for the company's internal usage Concentrator. Create interface on Altera and Xilinx FPGAs between E1/T1 channels and HPI port of TMS320CV5510 DSP using Quartus and ISE packages. Test board design for USB - via - RF interconnection. Writing Verilog code for Altera EPF10K10ATC144-1 FPGA, that should be used for configuration of "Intersil" base band processor, RF and IF parts, and also for the control of USB traffic. Design controller implemented in Altera EPF10K10ATC144-3 FPGA and support software package for programming Maxim DS2174 EBERT through RS232 interface. Sigma-Delta ADC: Design an IIR decimation filter. Design simulations were done using Mentor Modelsim and Tanner T-Spice simulators. P&R was made using Tanner L-Edit layout editor for HP 0.5um Fabrication process. ## Education ### Research Engineer in Post-Graduate School, Department of Physics and Microelectronics.Solid State State Engineering University, Yerevan, Armenia ### MS in Post-Graduate School, Department of Electronics State Engineering University, Yerevan, Armenia ### BA in Department of Semiconductor and Biomedical Devices, Faculty of Technical Cybernetics State Engineering University, Yerevan, Armenia ## Contact & Social - LinkedIn: https://linkedin.com/in/hrantmuradyan - Portfolio: http://www.synopsys.com --- Source: https://flows.cv/hrant JSON Resume: https://flows.cv/hrant/resume.json Last updated: 2026-04-13