Chief Computer Architect

Brought up efficiency of the design and DV teams. Optimized the design flow. Upgraded internal bus protocol.

Hands-on with coherent NoC fabric. Proxy Cache. In-depth knowledge in ARM CHI bus protocol.

Innovative memory architecture for HPC, servers, AI and other compute systems.

Wide-IO style custom DRAM as In-package memory. Custom DRAM controllers with CHI ports.

eDRAM Cache for massive bandwidth.

SoC design with ARM CMN fabric.

CXL Type III Memory Expander.

Lead 4 international sites to develop high-end, low-power, compact custom ARM cores, high-bandwidth memory subsystems and custom digital IPs of all sorts.

Hands-on with L0, L1, L2 coherent cache and in-package eDRAM cache.

Delivered a high-end, high efficient superscalar v7 ARM core. Led the teams from scratch to working silicon.

Built low-power design flow in the RTL stage.

Hands-on with computer arithmetic, multiplication, SRT division and square root.

Domain knowledge in branch predictors.