# Hunglin Hsu

> Total Compute System, Microprocessors, coherent fabric, memory controllers, eDRAM cache

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/hunglinhsu

## Work Experience
### Assistant General Manager @ MediaTek
Jan 2023 – Present | San Jose, California, United States
Chief Computer Architect

### VP of Engineering @ Arteris
Jan 2022 – Jan 2023 | Campbell, California, United States
Brought up efficiency of the design and DV teams. Optimized the design flow. Upgraded internal bus protocol.

Hands-on with coherent NoC fabric. Proxy Cache. In-depth knowledge in ARM CHI bus protocol.

### Sr. VP of Engineering @ FLC Technology Group
Jan 2018 – Jan 2022 | Santa Clara, California, United States
Innovative memory architecture for HPC, servers, AI and other compute systems.

Wide-IO style custom DRAM as In-package memory. Custom DRAM controllers with CHI ports.
eDRAM Cache for massive bandwidth.
SoC design with ARM CMN fabric.
CXL Type III Memory Expander.

### Vice President of Engineering @ Marvell Semiconductor Inc
Jan 2015 – Jan 2018 | Santa Clara, CA
Lead 4 international sites to develop high-end, low-power, compact custom ARM cores, high-bandwidth memory subsystems and custom digital IPs of all sorts.

Hands-on with L0, L1, L2 coherent cache and in-package eDRAM cache.

### Associate Vice President @ Marvell Semiconductor Inc
Jan 2013 – Jan 2015 | Santa Clara, CA
Delivered a high-end, high efficient superscalar v7 ARM core. Led the teams from scratch to working silicon.

Built low-power design flow in the RTL stage.

Hands-on with computer arithmetic, multiplication, SRT division and square root. 

Domain knowledge in branch predictors.

### Director Of Engineering @ Marvell Semiconductor Inc
Jan 2012 – Jan 2013 | Santa Clara, CA
Led the team in designing the next generation ARM cores from scratch. Built teams. Designed micro-architecture in the memory subsystem and the SIMD engine.

Delivered generations of memory controllers in working silicon.

Hands-on with out-of-order memory controllers.

### Staff Design Manager @ Marvell Semiconductor Inc
Jan 2009 – Jan 2012 | Santa Clara, CA
Built a memory controller logic design team. Delivered generations of memory controllers in the company. 

Built up a microprocessor memory subsystem team. Delivered a load-store unit with coherent cache.

### Sr. Staff Engineer @ Netronome
Jan 2008 – Jan 2009 | Santa Clara, CA
Worked on a DMA engine between the HAL interface of the Denali PCIe IP and the CPP interface of Intel.

Built descriptor queue, ingress and egress interfaces.

### Design Manager @ Marvell Semiconductor Inc.
Jan 2003 – Jan 2008 | Santa Clara, CA
Led the team in delivering an ARM v5 out-of-order microprocessor.

Designed MMU, AHB BIU and the embedded debugger.

### Design Engineer @ Sony Electronics
Jan 1999 – Jan 2002 | San Jose, CA
Clock tree analysis of Sony's MIPS microprocessor.

Designed a bus bridges to connect Sony's rendering engine to GPU and CPU.

Logic design. Synchronous and asynchronous clock domain crossing. FIFO management.

### Design Engineer @ Hitachi Micro System Inc.
Jan 1997 – Jan 1999 | San Jose, CA
Designed a radix-4 multiply-and-accumulate unit. Booth encoding. 4-to-2 and 3-to-2 compressors. Carry look-ahead adder. Design was done in schematics.


## Education
### MS in Electrical Engineering
University of Michigan

### BS in Electrical Engineering
National Cheng Kung University


## Contact & Social
- LinkedIn: https://linkedin.com/in/hunglin-hsu-069ab24

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Source: https://flows.cv/hunglinhsu
JSON Resume: https://flows.cv/hunglinhsu/resume.json
Last updated: 2026-04-13