# Igor Ziper

> ASIC, SoC, FPGA Design and Architecture

Location: Sunnyvale, California, United States
Profile: https://flows.cv/igorziper

SKILLS SUMMARY:
20+ years of Digital design experience in complex multi-million gate ASICs and SOCs;
Proficient in all aspects of the ASIC/SoC design flow: 
Analysis of architectural trade-offs based on features, performance requirements and system limitations;
Datapath and control path design, pipelining, low-power design, multi-clock domain design;
micro-architecture and design documentation;
RTL development and pre-/post-silicon debug;  
Implementation: synthesis, timing analysis and closure, clock domain crossing (CDC) analysis;
Acquired expertise in multiple areas while working on a broad list of IPs :
High-speed networking SOCs;
Machine Learning/ neural network/ High Level Synthesis with Cadence HLS-Stratus;  
ARM AXI/ACEL;
Security: encryption/authentication: AES/XTS/GCM/CBC/ECB; 
Scatter/Gather List (SGL) DMA operation;
SSD, NVMe, NAND Flash interface protocols;
FPGA based prototype development;
PCIe (PCI-Express).
AMBA fabrics and coherent interconnect
Strong communication and interpersonal skills, cross-functional team collaboration.

EMPLOYMENT HISTORY:
  Team Lead, Principal Engineer                        Microchip/Microsemi/PMC- Sierra/IDT(thru acquisitions)
  2000–Present                                                                                                           San Jose CA
-Machine Learning Accelerator for NAND management application: architected and developed a Neural Network(NN) Core for ML accelerator using High Level Synthesis with Stratus-HLS. Development of algorithm, RTL implementation/verification/synthesis
-Security Encryption Unit: architected and designed an authentication/encryption AES core (XTS/GCM), a key management, DMA engine with Scatter/Gather List support, Secure boot manager.
-Architecture development and RTL design of enterprise Flash memory controller: Simultaneous processing of Flash operations on multiple Flash channels, accelerators for HW RAID5/6 controller, buffer and power management.
-MIF -components for high performance communication of functional sub-systems/accelerators with on chip CPUs and ARM coherent interconnect (CCN-502).
-FPGA(Xilinx-Virtex5) based prototype of the Enterprise Flash Controller.
-PCIe Gen3-2-1 switches: full chip architecture definition, micro-architecture development and RTL design.

 ASIC Design Engineer                                                                       RAD Data Communication
 1994-2000                                                                                                               Tel Aviv, Israel

## Work Experience
### Sr. Tech Staff Eng - Digital Design, Product Dev @ Microchip Technology Inc.
Jan 2019 – Present | USA, CA, Sunnyvale

### Technical Ldr, Product Design @ Microsemi Corporation
Jan 2016 – Jan 2019 | USA, CA, Sunnyvale

### Technical Ldr, Product Design @ PMC-Sierra US Inc.
Jan 2013 – Jan 2016 | USA, CA, Sunnyvale

### Principal design engineer @ Integrated Device Technology Inc
Jan 2000 – Jan 2013


## Education
### Ben-Gurion University of the Negev

### Master of Science (MSc) in Computer Engineering
Tel Aviv University


## Contact & Social
- LinkedIn: https://linkedin.com/in/igor-ziper-4b90a28

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Source: https://flows.cv/igorziper
JSON Resume: https://flows.cv/igorziper/resume.json
Last updated: 2026-04-13