# Jack Z. Lin

> Principal Analog& Mixed Signal IP Design Engineer

Location: San Jose, California, United States
Profile: https://flows.cv/jackzlin

[S’99-M’01&03] Twenty-three years Mixed Signal IP Design, Integration, and Verification industry experience in Santa Clara County. Thorough understanding of integrated circuit CMOS design & layout techniques, as well as FINFET process technologies. Go through several product cycles and the silicon went into volume production for several customers in Wireless, Storage and Wireline application. Significant direct design experience of RX-ADC, TX-DAC, LO-PLL and DC reference generation design, verification and integration optimized of power, circuit performance and layout area for different application in the different process nodes 0.25um / 0.13um / 90nm / 65nm / 55nm / 40nm / 28nm / 22nm / 12nm / 7nm / 5nm / 4nm / 3nm crossing National [TI] / TSMC / IBM / Samsung / GF foundries. Experience with the standard SERDES like UCIE/Ethernet/MIPI/LVDS in both industry and class training. 
Experience with design and verification tools [Cadence Virtuoso IC design environment, analog circuit simulation tools like Spectre, Hspice, Finesim, RF design environment Keysight ADS, Layout verification tools like Caliber, Layout parasitic extraction toolset, EMX etcs]. 
My background includes scripting and programming languages which include Python, C etc. Understand how to model analog circuit behaviors using circuit abstraction tools like MATLAB, Verilog-AMS etc. Class training of Verilog and System-Verilog. Hand-on experience in using spectrum analyzers, oscilloscopes, signal generators, DC meter and network analyzer etc. to validate analog designs. Experience in working with test engineers for yield improvement and production issues. Experience in layout implementation at different process node. Concise and detailed documentation.
Domain expertise: 
Low Power Clock Distribution [PLL/DLL/PI/DCDL/CLKDIS] 
Low Speed High Resolution Analog Baseband Circuit [ADC/DAC/FILTER/LDO/DC2DC]	
Twenty years San Jose Evergreen residency, like hiking along the ocean and license to the light rock music. 
References upon request.

## Work Experience
### Principal Electrical Engineer @ Skyworks Solutions, Inc.
Jan 2024 – Present | 2740 Zanker Road, San Jose, CA, 95134
Continue to work upon analog, mixed-signal and RF IP development and grow my career

### Senior Staff Engineer, RF & Analog IC Design @ Samsung Semiconductor
Jan 2022 – Jan 2024 | 3655 North First Street, San Jose, CA 95134
Work upon cell level RF and Analog IC design.

### Senior Staff Engineer, Analog IC Design @ Marvell Technology
Jan 2012 – Jan 2022 | 5488 Marvell Lane, Santa Clara, CA 95054
Work upon IP development for Storage and Wireline communication application. 
Support Volume Production.

Z. Guo, A. Mostafa, A. Elshazly, B.Chen; B.Wang; C.Han; C.Wang; D.Zhou; D.Visani; E.Hsiao; F.Chu; F.Lu; G.Cui; H.Zhang; H.Wang; H.Zhao; J. Lin; J.Gu; L.Luo; L.Jiang; M.Singh; M.Gambhir; M.Hasan; M.Wu; M.J.Yoo; P.Liu; S.Kollu; T.Ye; X.Zhao; X.Yang; X.Han; Y.Huang; Y.Sun; Z.Yu; Z.H.Jiang; Z.Adal; Z.Yan. “A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET”, ISSCC, 2022

### Design Manager & Senior Engineer @ Augusta Technology USA, Inc.
Jan 2008 – Jan 2012 | 2933 Bunker Hill Lane, Suite 208, Santa Clara, CA 95054
Work with the digital design team and system architecture team to solve the IP integration problem. Work with the executive of the company to interface with the foundry TSMC, assistant in the silicon tape out, silicon fib & debugging and production testing of SOC for mobile application.

“Thin-oxide device protection circuits for data converters”, US Patent, 8259424

### Analog IC Design Engineer @ Broadcom Inc.
Jan 2004 – Jan 2008 | 3151 Zanker Road, San Jose, CA 95134
Work upon IP development for Wireless application.

Ali Afsahi; Jacob J. Rael; Arya Behzad; Hung-Ming Chien; Michael Pan; Stephen Au; Adedayo Ojo; C. Paul Lee; Seema Butala Anand; Kevin Chien; Stephen Wu; Rozi Roufoogaran; Alireza Zolfaghari; John C. Leete; Long Tran; Keith A. Carter; Mohammad Nariman; Keno Wai-Ki Yeung; Walter Morton; Mark Gonikberg; Mukul Seth; Marcellus Forbes; Jay Pattin; Luis Gutierrez; Sumant Ranganathan; Ning Li; Eric Blecker; Jack Lin; Tom Kwan; Rose Zhu; Mark Chambers; Maryam Rofougaran; Ahmadreza Rofougaran; Jason Trachewsky; Pieter Van Rooyen, “A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing an Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit”, IEEE Journal of Solid-State Circuits, Vol. 43, No. 5, May 2008
“On-Chip Current Sensing Methods and Systems”, US Patent, 7508188 & 7906955

### Intern, DFT Engineer @ National Semiconductor
Jan 2002 – Jan 2002 | 2900 Semoconductor, Santa Clara, CA 95052
2002, National 0.25um mixed-signal process: Project member of 1.2G LVDS 28-Bit FPD analog build-in-self-test project.


## Education
### MS in ECE
UC Santa Barbara

### MS and BS in Institute of Microelectronics and Engineering Physics
Tsinghua University


## Contact & Social
- LinkedIn: https://linkedin.com/in/jack-z-lin-40a34457

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Source: https://flows.cv/jackzlin
JSON Resume: https://flows.cv/jackzlin/resume.json
Last updated: 2026-04-13