Timing closure engineer and main liaison between front end design team and backend P&R group. Integrated the top level final timing signoff constraints. Owner of top level netlist synthesis and low power cell insertion. Also performed logical equivalence checking and low power(CPF/UPF) verification. Handled functional and timing ECOs. Created the LEC, STA, and RC extraction flows for Sigma set top box group. Wrote script generators for these flows. Mentored junior engineers in formal verification debugging, static timing analysis, and timing closure.
Responsible for RTL and testbenches for mixed signal mobile IoT(GPS tag) product consisting of RFIC and Baseband chips. Coordinated and verified design transfer from acquired company. Ported testbenches from VCS to NCSIM. Created C-code protocol oriented tests to be run on ATE and verified through RTL and gate simulation. Handled functional and timing ECOs for chip revisions. Owner of final timing closure and signoff.
