# James Gaba > "There's a way to do better - find it." - Thomas A. Edison Location: Sunnyvale, California, United States Profile: https://flows.cv/jamesgaba ASIC specialist passionate about creating state of the art mixed-signal SoCs at advanced process nodes. Excellent troubleshooting, communication, and leadership skills. Core competencies include SoC integration, RTL and constraints qualification, synthesis, logical equivalence checking, low power cell insertion, low power verification, timing analysis and closure. Experienced with entire RTL to GDS CAD flow. Strong background in software allows me to maximize efficiency in CAD flows through customized tool scripting on top of baseline flows. Solid understanding of timing concepts including SI effects, noise glitch repair, clock skew, OCV, process variation, RC extraction, and backend P&R flow. Systematically debugged many complex LEC issues whose root cause may be tool, HDL, or library related. High familiarity with tool capabilities and limitations allows me to qualify new RTL and constraints in order to reduce schedule risks. Areas of interest: EDA, computer networks, and embedded systems. ## Work Experience ### Principal Application Engineer @ Synopsys Inc Jan 2018 – Present | Mountain View, CA Timing and power signoff ### Sr. Manager ASIC Design @ Sigma Designs Jan 2013 – Jan 2017 | Fremont, CA Timing closure engineer and main liaison between front end design team and backend P&R group. Integrated the top level final timing signoff constraints. Owner of top level netlist synthesis and low power cell insertion. Also performed logical equivalence checking and low power(CPF/UPF) verification. Handled functional and timing ECOs. Created the LEC, STA, and RC extraction flows for Sigma set top box group. Wrote script generators for these flows. Mentored junior engineers in formal verification debugging, static timing analysis, and timing closure. Responsible for RTL and testbenches for mixed signal mobile IoT(GPS tag) product consisting of RFIC and Baseband chips. Coordinated and verified design transfer from acquired company. Ported testbenches from VCS to NCSIM. Created C-code protocol oriented tests to be run on ATE and verified through RTL and gate simulation. Handled functional and timing ECOs for chip revisions. Owner of final timing closure and signoff. ### Sr Staff ASIC Design Engineer @ Sigma Designs Jan 2011 – Jan 2013 | Fremont, California Timing Signoff/Timing Closure/RC Extraction Low Power Methodologies Synthesis and Logical Equivalence RTL design/simulation CAD tool evaluation and recommendation ### Sr. ASIC Design Engineer @ Sigma Designs Jan 2007 – Jan 2011 ### Sr. Product Engineer @ Magma Design Automation Jan 2005 – Jan 2007 ### Sr. Applications Engineer @ Magma Design Automation Jan 2003 – Jan 2005 Performed technical evaluation for companies of various sizes from startup to large sized companies including Cisco and Broadcom. Worked closely with sales account manager to formulate sales strategies. Trained and supervised junior applications engineers in post-sales account support. In pre-sales role, engaged with customer to discover needs and how Magma software could benefit. Provided mentoring and leadership to regional junior applications engineers. Established several IC implementation flows with differing requirements. Created automated software QA suite for regional synthesis group. Worked closely with marketing to define use models. Worked closely with R&D to implement new features. Conducted monthly training for Magma’s physical synthesis tool – Blast Create. Created automated TCL scripts to accelerate adoption of formal tool - QuartzFormal. ## Education ### BS in Electrical & Computer Engineering - Emphasis on Software Analysis and Design Carnegie Mellon University ### MS in Computer Engineering - Emphasis on Video Compression and DSP Santa Clara University ## Contact & Social - LinkedIn: https://linkedin.com/in/james-gaba-1851a01 - Portfolio: http://www.sigmadesigns.com/ --- Source: https://flows.cv/jamesgaba JSON Resume: https://flows.cv/jamesgaba/resume.json Last updated: 2026-04-13