● Lead and own DDR sub-system in SoC Yitian-710

○ Define u-Arch of DriveWay module to support TrustZone filter, Channel de-interleaving, address remapping and hashing functions, with standard CHI interfaces.

○ Integrate DDR sub-system into SoC and work closely with backend to solve all the timing issues on the interface.

● Define u-Arch of fully customized DDR5 controller for next generation Yitian SoC

○ Define u-Arch from scratch to optimize for low latency

○ Fully customized for specific function requirements from next generation Yitian SoC

○ Target to support DDR5-7200 in TSMC N3 process

Principle Engineer, IoT & Infrastructure Platform Architecture (IIBU)

● Define CPU subsystem architecture for Renesas Advanced (RA) MCU platform

○ Analyze Cortex-M33 performance/area/cost with different cache configurations and BUS

topologies.

○ Analyze and propose improvement of flash cache for embedded flash subsystem.

○ Define power domains and power modes in CPU subsystem, targeting both low power and low

wake-up latency.

Ethernet MAC IP design engineer, Programmable Solution Group(PSG)

● Define micro-architecture and RTL design of 400G Ethernet MAC IP

○ Fully configurable to support different Ethernet speed from 10Gbps to 400Gbps.

○ Fully compatible with IEEE 802.3-2015 and IEEE 802.3bs standard

5G Modem SoC design engineer, Next-Generation-Standard (NGS)

● Integrate 3rd party IPs into 5G modem SoC, including Cortex-A53, ARM Generic-Interrupt-Controller (GIC-500) and Cadence LPDDR4 memory controller.

● Design wrappers for 3rd IPs to fit the requirement of the SoC.

○ Add Dynamic-Frequency-Scaling (DFS) control for Cadence memory controller to interface with PMU.

○ Add interrupt source polarity control in GIC.

○ Add varies asynchronous bridges in Cortex-A53 to interface varies SoC part: Fabric, CoreSight, etc.

● Work closely with verification team to provide the 3rd party IP support.