# Jason Xu > Principal RTL Engineer at Ambiq Micro Location: San Jose, California, United States Profile: https://flows.cv/jasonxu1 Seeking new opportunities and challenges in digital IP or SOC design. • Over 30 years of semiconductor industry experience, including over 20 years in ASIC and digital design • Expertise in Verilog HDL, perl, tcl and shell scripting • Expertise in ARM AMBA system (CHI, ACE, AXI, AHB, APB) • Expertise in memory controller design. Extensive knowledge on DDR4/DDR5/LPDDR3/LPDDR4/WideIO/WIO2/HBM • Familiar with Synopsys DC/DCT/PT/VCS/Formality, Cadence NC-verilog,/verilog-xl/Conformal, Verdi, Denali etc. Specialties: ARM based SOC, AMBA, CHI, AXI, AHB, APB, ACE, Memory Controller, DDR/DDR2/DDR3/DDR4/DDR5/LPDDR/LPDDR2/LPDDR3/LPDDR4/WideIO/WIO2/HBM ## Work Experience ### Principal RTL Engineer @ Ambiq Jan 2022 – Present | San Francisco Bay Area ### Senior Staff Engineer @ Alibaba Group Jan 2020 – Jan 2022 | United States ● Lead and own DDR sub-system in SoC Yitian-710 ○ Define u-Arch of DriveWay module to support TrustZone filter, Channel de-interleaving, address remapping and hashing functions, with standard CHI interfaces. ○ Integrate DDR sub-system into SoC and work closely with backend to solve all the timing issues on the interface. ● Define u-Arch of fully customized DDR5 controller for next generation Yitian SoC ○ Define u-Arch from scratch to optimize for low latency ○ Fully customized for specific function requirements from next generation Yitian SoC ○ Target to support DDR5-7200 in TSMC N3 process ### Principal Engineer @ Renesas Electronics Jan 2018 – Jan 2020 | Milpitas, California Principle Engineer, IoT & Infrastructure Platform Architecture (IIBU) ● Define CPU subsystem architecture for Renesas Advanced (RA) MCU platform ○ Analyze Cortex-M33 performance/area/cost with different cache configurations and BUS topologies. ○ Analyze and propose improvement of flash cache for embedded flash subsystem. ○ Define power domains and power modes in CPU subsystem, targeting both low power and low wake-up latency. ### FPGA IP Design Engineer @ Intel Corporation Jan 2017 – Jan 2018 | San Jose, CA Ethernet MAC IP design engineer, Programmable Solution Group(PSG) ● Define micro-architecture and RTL design of 400G Ethernet MAC IP ○ Fully configurable to support different Ethernet speed from 10Gbps to 400Gbps. ○ Fully compatible with IEEE 802.3-2015 and IEEE 802.3bs standard ### 5G Modem SoC design engineer @ Intel Corporation Jan 2016 – Jan 2017 | Santa Clara, California 5G Modem SoC design engineer, Next-Generation-Standard (NGS) ● Integrate 3rd party IPs into 5G modem SoC, including Cortex-A53, ARM Generic-Interrupt-Controller (GIC-500) and Cadence LPDDR4 memory controller. ● Design wrappers for 3rd IPs to fit the requirement of the SoC. ○ Add Dynamic-Frequency-Scaling (DFS) control for Cadence memory controller to interface with PMU. ○ Add interrupt source polarity control in GIC. ○ Add varies asynchronous bridges in Cortex-A53 to interface varies SoC part: Fabric, CoreSight, etc. ● Work closely with verification team to provide the 3rd party IP support. ### Memory Sub-System Architect @ Marvell Semiconductor Jan 2013 – Jan 2016 ●Define and design 6th generation McKinley family memory controller, Quad-channel McKinley 6, including new micro-architecture and RTL design. The memory controller supports DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4. The target speed is up to 1.2GHz clock speed. ○Design a brand new architecture to improve performance. ○Design a “pool” instead of “queue” to further improve DDR scheduling and efficiency. ○Design a mechanism to forward or merger data from internal data buffer. ○Design a 2-stage scheduler to balance speed and performance. ●Co-design Final-Level-Cache (FLC) micro-architecture. Define the interface and handshake between FLC and memory controller. ### Design Manager @ Marvell Semiconductor Jan 2011 – Jan 2013 ●Define and design 5th generation high performance dual-channel memory controller McKinley 5, including micro-architecture and RTL design. The memory controller supports DDR3/DDR4/LPDDR2/LPDDR3. The target speed is up to 1.2GHz clock speed. ○Change architecture based on previous generation memory controller McKinley 4 to support dual-channel. ○Doubled parallel queue number to improve DDR efficiency. ### Staff Engineer @ Marvell Semiconductor Jan 2009 – Jan 2011 ●Design high performance out-of-order execution memory controller McKinley 4, including architecture and RTL. The memory controller supports DDR/DDR2/DDR3/LPDDR/LPDDR2/LPDDR2-NVM. The target speed is up to 1.2GHz clock speed. ○Define out-of-order memory controller architecture from scratch ○Design mechanism of re-ordering-buffer to re-order requesting data before sending back to the requesters. ○RTL design for all command handling: arbitrate between 8 individually configurable master ports, dispatch the commands into 8 parallel queues, generate DDR BUS commands from queues, and schedule DDR BUS commands from 8 queues. ○RTL design configuration registers, user initiated DDR command, DDR configuration and maintenance requests and DDR power feather handling logic. ○RTL design DDR timing control logic. ○Create and maintain the module level verification environment. ### Sr. Design Engineer @ Marvell Semiconductor Jan 2006 – Jan 2009 • Design low latency in-order memory controller Mckinley3. The memory controller supports DDR/DDR2/DDR3/LPDDR/LPDDR2. The target speed is 400MHz clock speed. o RTL design for all command handling: arbitrate between 4 master ports, dispatch the commands into 4 serial queues, generate DDR BUS commands from queues, and schedule DDR BUS commands from queues. o RTL design DDR maintenance requests and DDR power feather handling logic. o RTL design DDR timing control logic. • Design AHB wrapper to convert AHB-lite master to AHB-full master. • Maintain/Enhance/Support in-house designed ARM9 CPU. ### Sr. Design Engineer @ Rohm Electronics Jan 1996 – Jan 2006 • Work on ARM based SOC projects: DVD A/V decoder, CD MP3 decoder • Develop ARM AMBA AHB and APB peripherals: TIMER, WDT (Water Dog Timer), GPIO, GIR (Generic Infrared Interface), internal memory interface, external DRAM interface, NOR flash interface, UART, and CPRM (Content Protection for Recordable Media). Tasks include creating specifications, RTL coding with Verilog HDL, verification with Cadence NC-verilog, debugging with Novas Debussy, and synthesizing with Synopsys Design Compiler • Develop NOR flash behavior simulation model with Verilog HDL • Develop AMBA AHB BFM to simplify the AMBA peripheral simulations • Integrate and validate IPs into ARM AMBA system • Develop Semaphore module to communicate between 2 ARM CPUs • Verify system integration on the SOC level using ARM assembly codes • Integrate IPs into customer ASIC designs • Retarget FPGA designs to ROHM ASIC designs ## Education ### BSEE in Electrical and Electronics Engineering Fudan University ## Contact & Social - LinkedIn: https://linkedin.com/in/jasonxu2 --- Source: https://flows.cv/jasonxu1 JSON Resume: https://flows.cv/jasonxu1/resume.json Last updated: 2026-04-12