# Jasopin Lee > Principal Consultant Location: Sunnyvale, California, United States Profile: https://flows.cv/jasopin Enabling DataCenter AI/ML GPU, Consumer Electronic SoC, wearable device, Internet of thing (IoT) and Smart Energy Management applications through Advance Semiconductor Design: Chiplet+Processor+Sensor+Wireless Network. A Senior Management and Entrepreneur with experience in High Performance Circuit (HPC), Low Power Mobile Processor, High Voltage Driver, Multimedia, IP, SoC, ASIC, DFT, SERDES, Advance Technology and Advance 3/2.5D Packaging Technology. Specialties: SoC development Management, IP Management, Management Consultancy, ODM/OEM management, Foundry Management, OSAT Management and Program Management. Intel Trained Systematic Project Management, Strategic Partnership Management, and International ODM/OEM Management Experience. ## Work Experience ### Principal Consultant @ Unknown Jan 2023 – Present I provide IP, SoC, technology, advanced packaging, DTCO/STCO and phase gate methodology consultation services I also participate some angel investment opportunities ### Member Board Of Directors @ CHINESE INSTITUTE OF Engineer/USA San Franscisco Jan 2021 – Present | United States ### Board of Volunteer @ Chinese American Semiconductor Professional Association Jan 2006 – Present Special Interest Group and Seminar (mobile Processor, Auto IC, CleanTech and New Energy) Business Development Have been a CFO, Board of Director, hosted Symposium and Seminars. ### Sr IP and SoC Technical Program Manager @ Amazon Lab126 Jan 2022 – Jan 2023 | United States Arm Core, Security, Crypto, Display, Video, uController, ISP IPs management Next generation SoC management ### Senior SoC and Chiplet Engineering Program Manager @ AMD Jan 2013 – Jan 2021 | Sunnyvale, CA, USA SoC Program Management, design methodology, milestones/checkpoints and design maturity. IP management - core, foundation, mixed mode, connectivity and multimedia IPs Cross Functional management, partnership, interlock, communication and bridging. Advance 5nm, 7nm, 12nm and 14/16nm technologies. Fanout and CoWoS 2D/2.5D/3D advanced packaging Technologies Silicon area reduction and cost saving analysis. ### Technology Adviser, Consultant and Entrepreneur @ Technology and Project Management Jan 2009 – Jan 2013 I supported or was working on: * Advised clients as subject matter expert on ARM mobile SoC, mix-mode design, product definition, design flow, quality, test, and improvement plan for Application Processor (AP), Tablet Display Controller and mixed mode IPs * Solid State High Voltage Driver and Smart Sensor for SmartHome/SmartBuilding applications. * Advance Sensors (image/IR sensor, MEMS Gyro, Accelerometer, eCompass) for Internet of Things (IoT) and wearable devices. Architected and supported ASIC designs. ### ASIC Driver Program and Camera Project Manager Consultant @ LensVector Jan 2009 – Jan 2011 | Mountain View, CA Managed three high voltage LensVector Auto Focus (LVAF) lens ASIC driver IC programs, including mixed mode ASIC design, 0.18um high voltage technology, CSP/QFM/Flip-Chip packaging technology, flexible circuit, manufacture, test and operation logistic supports. Completed an AutoFocus webcam ODM/OEM project, including lens and housing procurement, image sensor, ISP & USB controller interface, camera system integration, calibration and and test. Managed and supported WLCSP, flip-chip packaging technologies and fine-pitch flexible circuit. ### 45nm Technology Program Manager @ Qualcomm, QCT Jan 2007 – Jan 2008 Managed 45nm program including two and half 3G mobile CPU designs, IPs, tapeout, test, process technology and a first-call system demonstration. Managed cross-functional core teams to execute key strategies/tactics and deliverables. ### Director, Design Service and Engineering @ GLOBALFOUNDRIES (Chartered Semiconductor) Jan 2005 – Jan 2006 Established an US ASIC Design Service Center and managed EDA alliance, IP portfolio, licensing and procurement program (at US and Singapore). Supported pre-sale customer enablement and foundry business development. Supported and managed CDMA mobile SoC and OLED driver SoC projects, 65nm 16M SRAM testchip, high performance SRAM, eFuse and mixed signal IP development; provided customer support, licensing and program management. Supported and managed 45nm testchip and IP development. ### Sr Director, CPU Design Engineering @ Arcadia Design Systems Jan 2001 – Jan 2004 | San Jose, California Booked, planned and managed a Sever CPU design contract, and managed business relationship. Architected a 500MHz to 3GHz UltraSparc-V Server CPU design and methodology, conducted a feasibility study and obtained a buy-in from customer. Managed micro-architecture, logic design, circuit design, physical design, and verification, including testchip validations for Floating Point Unit, Graphical Unit, and level one&two cache SRAMs Managed and supported TSMC 0.13um, IBM 130nm SOI & 90nm SOI and Fujitsu 85nm technologies for high performance circuit library, parity generation/check circuit, datapath circuit, cache SRAM and dual-port RAM. ### Sr Manager, Memory & Circuit Design @ Texas Instruments (National Semiconductor) Jan 1998 – Jan 2001 Managed design and development of custom memory macros and compilers of SRAM, dual-port RAM, ROMs, NVM memories, circuit library and Datapath Multiplier for SiTel telephone, automobile ABS controller, DVD decoder IC, OFDM network processor, X86 CPU Core, Power, Analog and government projects. Managed suppliers of memory, datapath circuit and EDA tools, including memory compiler, hierarchical verification flow, circuit simulator/debugger and SST Flash memory technology transfer. ### Manager, ASIC Circuit Design @ LSI Logic Jan 1993 – Jan 1997 Designed DSP Motion Estimator (video compression) with 64-processor array CPU, including custom datapath circuit core, timing closure, and full-chip ASIC physical design to tapoeut. Designed 0.5 & 0.35um CMOS standard cell, IO, ESD libraries, USB 1.0/1.1 PHY, impedance-match PVT compensation and high speed DDR IOs. Led a a Process Portable circuit library design program. Member of PlayStation 1, Eagle, Cray YMP, design, debug and support teams. ### Senior Engineer, P5 MCM and Design Technology @ Intel Jan 1990 – Jan 1993 Developed a "Boundary Scan Test System" to test i486(tm) MCM & MPM modules, including software and system PCB designs. Participated IEEE 1149.1 (JTAG) standard committee. Designed custom datapath circuits, large drive strength buffers, tri-state drivers, latches, CMOS and BiNmos circuits for P5 and P6. Supported i486 processor synthesis development for timing and new area reduction objectives, tested and resolved timing closure problems. ### Engineer II, ASIC Design @ VLSI Technology Jan 1988 – Jan 1990 Developed a full scan EDA software and conducted scan insertion, test vectors and programs' generation, (sequential) scan test vector conversion, design verification, fault grading and ATE test for a Harris military DSP design. Developed a IEEE 1149.1 (JTAG) boundary scan test CAE tools. Supported EDA software development to convert simulation vectors to ATE test vectors and programs. ## Education ### MBA in Business Adminstration CALMAT ### B.S. Engineering National Cheng Kung University ### M.S. in ECE UC Santa Barbara ## Contact & Social - LinkedIn: https://linkedin.com/in/jasopin-lee-84970ab --- Source: https://flows.cv/jasopin JSON Resume: https://flows.cv/jasopin/resume.json Last updated: 2026-04-13