System EE Technical Lead

Led a team of 12 engineers during the NPI product development of a MacBook Air.

System EE Technical Lead

Main logic board lead managing schematic integration and layout.

Led a team of 12 engineers during the NPI product development of a MacBook Air.

Main logic board lead managing schematic integration and layout.

Reference design schematic owner for SOC, Display Backlight, Display PMIC, Gyroscope/Accelerometer, and SSD sub-systems.

Schematic integrator for main logic board.

Schematic design and layout of audio speaker amplifier and CODEC board.

Designed several 2- and 3-layer flexible printed circuit boards.

Designed and validated thermal and power sensors for main logic board.

Schematic integrator for main logic board.

Designed and validated thermal and power sensors for main logic board.

Developed boards to enable bring-up of new CPU architectures.

Co-designed an embedded system which employed PCIe Gen 2 x2, NVMe (PCIe Gen 3 x4), and DDR3L SDRAM interfaces which interfaced to an Intel/Altera Arria 10 GX FPGA.

Designed a 100MHz reference clock generation and distribution network, which originated from a 25MHz TCXO and supported SSC.

Architected a method for robust field upgrade of an FPGA deployed in space.

Led training sessions on the mechanics of FPGA design and simulation.

Presented paper entitled "A Method for Storing Semiconductor Test Data to Simplify Data Analysis"​ at the IEEE AUTOTESTCON 2016 conference in Anaheim, CA.

Collaborated with the Keysight Technologies Spectrum Analyzer Division on a new feature for the X-Series Signal Analyzers. Work included porting a DSP IP block from a Xilinx Virtex-4 FPGA to a Xilinx Kintex UltraScale FPGA and documenting improvements. The DSP IP block ran at a clock frequency greater than 300MHz.