# Jeremy Webb > Principal Design Engineer at Apple Location: San Francisco Bay Area, United States Profile: https://flows.cv/jeremywebb Energetic Principal Design Engineer with a focus on high-speed digital design and FPGA development. Consistently delivers creative, high performance solutions in the fields of test and measurement and video/image processing. Special interest in Bit Error Ratio Tester, Spectrum Analyzer, and Arbitrary Waveform Generator architectures. A driven engineer who enjoys tackling design dilemmas that result in superior product performance. Specialties: High-Speed FPGA Design; PC Board Design; HDL Design: SystemVerilog, Verilog HDL, and VHDL; Perl programming; Matlab programming ## Work Experience ### Principal Design Engineer, MacBook Air Hardware Technical Lead @ Apple Jan 2023 – Present | Cupertino, California, United States 2026 13" and 15" MacBook Air (3/2026) • System EE Technical Lead • Led a team of 12 engineers during the NPI product development of a MacBook Air. 2024 13" and 15" MacBook Air (3/2024) • System EE Technical Lead • Main logic board lead managing schematic integration and layout. • Led a team of 12 engineers during the NPI product development of a MacBook Air. ### Senior Design Engineer, MacBook Air Hardware Technical Lead @ Apple Jan 2022 – Jan 2023 | Cupertino, California, United States ### Senior Design Engineer, MacBook Air MLB Lead @ Apple Jan 2017 – Jan 2022 | Cupertino, California 2022 13" MacBook Air (6/2022) • Main logic board lead managing schematic integration and layout. • Reference design schematic owner for SOC, Display Backlight, Display PMIC, Gyroscope/Accelerometer, and SSD sub-systems. 2020 13" MacBook Air (11/2020) • Schematic integrator for main logic board. • Schematic design and layout of audio speaker amplifier and CODEC board. • Designed several 2- and 3-layer flexible printed circuit boards. 2020 13" MacBook Air (3/2020) • Designed and validated thermal and power sensors for main logic board. • Schematic integrator for main logic board. 2019 13" MacBook Air (refresh; 7/2019) 2018 13" MacBook Air (10/2018) • Designed and validated thermal and power sensors for main logic board. • Developed boards to enable bring-up of new CPU architectures. ### Senior FPGA Engineer/Technical Lead @ Planet Jan 2017 – Jan 2017 | San Francisco, California • Developed an automated build and simulation environment for FPGA design using Perl, Bash, Makefiles, and Tcl. • Co-designed an embedded system which employed PCIe Gen 2 x2, NVMe (PCIe Gen 3 x4), and DDR3L SDRAM interfaces which interfaced to an Intel/Altera Arria 10 GX FPGA. • Designed a 100MHz reference clock generation and distribution network, which originated from a 25MHz TCXO and supported SSC. • Architected a method for robust field upgrade of an FPGA deployed in space. • Led training sessions on the mechanics of FPGA design and simulation. ### Principal Engineer @ J. Webb Consulting Jan 2013 – Jan 2017 | St Helena, California, United States • Collaborated with the Keysight Technologies Oscilloscope Product Division and the Keysight Laboratories group on a new feature for their high performance oscilloscopes. Work included developing a new control pc board along with FPGA design targeting a Xilinx Artix-7 FPGA and documenting calibration procedures. • Presented paper entitled "A Method for Storing Semiconductor Test Data to Simplify Data Analysis"​ at the IEEE AUTOTESTCON 2016 conference in Anaheim, CA. • Collaborated with the Keysight Technologies Spectrum Analyzer Division on a new feature for the X-Series Signal Analyzers. Work included porting a DSP IP block from a Xilinx Virtex-4 FPGA to a Xilinx Kintex UltraScale FPGA and documenting improvements. The DSP IP block ran at a clock frequency greater than 300MHz. ### Senior Engineer @ Microsemi Corporation Jan 2014 – Jan 2016 | Santa Rosa, CA Centellax was acquired by Microsemi Corporation. Developed a digital bias control ASIC on the IBM 8HP BiCMOS SiGe process. The digital bias control ASIC contained a serial peripheral interface (SPI) for accessing the register interface, a 10-bit Delta-Sigma DAC, and supported channel identification when deployed in a multiple channel configuration. The design was implemented using System Verilog, and the Cadence Encounter, RTL Compiler, and Incisive software suites. Continued the development of Microsemi's central test database by adding support for all surface mount products and adding capability to store wafer test data from new foundries. Developed yield reporting tools to support planning, R&D and production with accessing data from the central database. The entire system was developed using Linux, Apache, MariaDB, Perl, Git, Javascript, HTML5, and CSS. ### Senior Engineer @ Centellax Jan 2013 – Jan 2014 | Santa Rosa, CA Led a project to consolidate wafer foundry PCM and Centellax production test data into a central database. This project accelerated identification of wafer performance deviations and streamlined its ability to track performance across all Centellax products from wafers and IC die to finished goods. Developed reporting tools to support planning, R&D and production with accessing data from the central database. The entire system was developed using Linux, Apache, MariaDB, Perl, Git, Javascript, HTML5, and CSS. ### Senior Design Engineer @ Agilent Technologies Jan 2012 – Jan 2013 | Santa Rosa, CA • Agilent Technologies acquired the Centellax Test and Measurement Division in May 2012. • Led the migration and integration of all Centellax T&M IT equipment into the Agilent IT infrastructure. • Identified cross-reference matches between Agilent and Centellax internal part numbers via automated Perl scripts to minimize new part number setup and allow better integration of Centellax T&M bill of materials within the Agilent ERP systems. • Deployed Perl CGI websites to aid in bill of material generation and searching of Agilent and Centellax cross-referenced part numbers. • Designed a USB 2.0 FPGA IP core for controlling FPGA based Test and Measurement Equipment. • Architected a solution for automating 16:1 multiplexer and 1:16 demultiplexer IC testing, data storage, retrieval, and analysis to aid with the pass/fail selection process. • Developed an automated characterization test for an amplifier IC to better understand its broadband performance prior to its use on a high performance 32Gb/s Programmable Pattern Generator. ### Senior Design Engineer @ Centellax (Test and Measurement Division) Jan 2007 – Jan 2012 | Santa Rosa, CA • Designed the Data Path FPGAs for the PG32 32Gb/s Programmable Pattern Generator and ED32 32Gb/s Programmable Error Detector PODs. The Data Path FPGAs operate at speeds up to 1Gb/s, interface with 4 16:1 Multiplexers and 1:16 Demultiplexers operating at 8Gb/s, and generate both Pseudo-Random Binary Sequences and custom user patterns. • Architected the Data Path FPGAs for the PPG12500 10Gb/s Programmable Pattern Generator and PED12500 10Gb/s Programmable Error Detector. The Data Path FPGA operates at speeds up to 1Gb/s, interfaces with 36Mb of QDR-II SRAM operating at 500Mb/s, and generates both Pseudo-Random Binary Sequences and custom user patterns. • Designed the Xilinx MicroBlaze Hardware Architecture used on digital sub-systems. The MicroBlaze 32-bit processors had many peripherals including a 512Mb 125MHz DDR2 SDRAM, 2GB microSD card, and 64Mb SPI Flash PROM. • Documented FPGA and PC board designs using a combination of an internal wiki and website and an engineering reference specification. The documents contained information on design intent, control algorithms, register definitions, and hardware modifications. • Performed software design of control algorithms using C code for loading patterns and capturing data. The C code interfaced to a Xilinx Virtex-5 FPGA via a 32-bit MicroBlaze processor running in a Xilinx Spartan-3A DSP FPGA. • Managed the development effort for an external PC application used to load custom patterns onto Centellax PPG12500, PED12500, and SSB16000J products. Specified requirements for software functionality and user interface design. • Created a web based search utility to simplify company-wide part searches using a combination of Perl DBM and CGI. • Streamlined new part number requests by implementing a web-based submission form which automatically distributed the part information to the appropriate departments and personnel. As a result, part setup mistakes on printed circuit boards and mechanical drawings were minimized. ### Research Assistant @ University of California, Davis Jan 2003 – Jan 2011 | Davis, CA • Architected a configuration interface for a first- and second-generation multi-core processor. • Developed a website to document the progress and design process of my Master’s thesis project. Created a Subversion revision control repository for tracking all design files from PC board schematics to SystemVerilog code for FPGA designs. • Mentored several undergraduate students in various disciplines including embedded software design, FPGA design, and PC board design. • Consulted for several UC Davis research groups including the Chemistry Department, the Mechanical Engineering Department, and the Optical Research Group. Provided information regarding FPGA and embedded software design. • Developed a general purpose instrument for testing and characterizing a high performance DSP chip, known as AsAP, when performing real world DSP tasks. The baseband instrument has a bandwidth of 120 MHz, and can generate and analyze sine, triangle, square, and arbitrary waveforms. The signal source frequency domain specifications include an SFDR of 68 dBc, SNR of 101 dBc, and a TOI of 26.58 dB at -6 dBFS for sine waveform outputs. ### Digital Hardware Engineer @ Agilent Technologies Jan 2004 – Jan 2007 | Santa Rosa, CA • Implemented a high-performance numerically controlled oscillator for a Direct Digital Clock Synthesizer in a Xilinx Virtex II and Virtex-4 FPGA. • Performed schematic design for a high-performance Spectrum Analyzer Motherboard. • Proposed and built an RS-232 Hub/SPI Controller board for a high-performance Spectrum Analyzer. This board allowed for faster debug and turn-on of SA Measurement boards. • Responsible for multiple complex designs targeting multi-million gate FPGAs. • Led the schematic design and layout of the analog section of a new measurement board for a high-performance Spectrum Analyzer, thus accelerating the schedule by 2 months. • Designed the control FPGA and PC Board of the N9010A EXA low-cost Front End. ### Digital Hardware Engineer @ Thomson Grass Valley Jan 2004 – Jan 2004 | Nevada City, CA • Designed FPGAs for mix effects television production equipment such as the Kayak HD/SD switcher and Kalypso Video Production Center. ### Digital Hardware Engineer @ Barco Jan 2004 – Jan 2004 | Rancho Cordova, CA • Barco purchased Folsom Research in January 2004. • Scoped out control FPGA design for the MatrixPRO Digital Series video matrix switchers. • Designed the Control FPGA for the Encore Presentation System Large and Small Controllers. • Designed the Control PC Board for the Encore Presentation System Large and Small Controllers. • Designed the single-board computer for the Encore Presentation System. ### Digital Hardware Engineer @ Folsom Research, Inc. Jan 2003 – Jan 2004 | Rancho Cordova, CA • Assisted with Schematic design for the ImagePRO Video Scaler. • Designed the control FPGA for the MatrixPRO Analog Series video matrix switchers. • Re-designed a phase-locked loop circuit for a serial digital interface (SDI) serializer chip. The existing design had significant clock to data jitter that was noticeable to customers. The new design significantly decreased the jitter, and eliminated all errors in the data transmission. • Designed the control FPGA for the Encore Presentation System Large and Small Controllers. • Designed the control pc board for the Encore Presentation System Large and Small Controllers. • Designed the single-board computer for the Encore Presentation System. ### Manufacturing Hardware Engineer @ Agilent Technologies Jan 2001 – Jan 2002 | Santa Rosa, CA • Served as the lead Manufacturing Engineer for both the N1015A Modulation test set and the 71501D Jitter Analysis System. • Assisted with environmental qualification and testing of the N1015A. • Worked closely with the Design For Manufacturing group to upgrade HP3070 tests performed on the pc boards in Agilent’s 86130A BitAlyzer. Test upgrades improved pc board yields by 30%. • Analyzed and revised test specifications for pc boards used in both Agilents 86130A BitAlyzer and N1015A Modulation test set. Designed test set documents and procedures for production line tests. • Performed initial turn-on and debugging of the Analog Mother board for the 13 Gb/s BERT, and discovered a power-plane design flaw which would have prevented the BERT from functioning. • Trained technicians on troubleshooting to reduce scrap costs. • Performed extensive system troubleshooting to determine root cause of various hardware and software bugs in Agilent’s 86130A BitAlyzer. ### Digital Hardware Engineer @ Agilent Technologies Jan 2001 – Jan 2001 | Santa Rosa, CA • Co-designed the controller pc board and FPGA Verilog HDL core for the N1016A 10 Gigabit Ethernet Stressed Eye test set. The FPGA Verilog HDL core interfaced with DACs and ADCs, a serial EEPROM, microwave switches, and rotary pulse generators. This was the only solution in the world to be 100% compliant with 802.3ae clause 52. • Designed and manufactured a demonstration tool (JET) for Agilent’s 86130A BitAlyzer. The project involved pc board and FPGA Verilog HDL core design using Xilinx Spartan II FPGAs. The JET helped to increase customer understanding of the BitAlyzer's Error Analysis Software and resulted in increased sales. • Presented a poster paper on the effectiveness of Agilent’s 86130A Error Analysis software at the Optical Network Interface Design Symposium 2002 in San Jose, CA. http://jwebb-design.com/pubs/ ### SEED Student (Level II) @ Agilent Technologies Jan 2000 – Jan 2000 | Santa Rosa, CA • Worked with the Software Quality Engineering group performing software regression tests on the 3Gb/s Serial BERT. • Co-designed and assembled a 10 GHz phase-locked YIG signal source. Involved designing C and Assembly language software modules to interface a PIC microprocessor, DACs, and a fractional-n synthesizer. ### Research Assistant @ UC Davis Jan 1999 – Jan 2000 | Davis, CA • Developed a bit error ratio tester platform, based on a Dallas Semiconductor DS2172 BERT IC, for an optics laboratory. The BERT platform was used by students to verify the performance of optical-to-electrical and electrical-to-optical devices at data rates up to 50Mb/s. ## Education ### Electrical and Electronics Engineering University of California, Davis Jan 2011 – Jan 2017 ### MSEE in Electrical Engineering (DSP) University of California, Davis Jan 2003 – Jan 2011 ### BSEE in Electrical Engineering University of California, Davis ## Contact & Social - LinkedIn: https://linkedin.com/in/jeremywwebb - Portfolio: http://jwebb-design.com - Portfolio: https://jwebb-consulting.com - Portfolio: https://msee.jwebb-design.com/measbd/ --- Source: https://flows.cv/jeremywebb JSON Resume: https://flows.cv/jeremywebb/resume.json Last updated: 2026-03-30