Principal Memory Design Engineer & AI Hardware Lead with 30+ years of expertise in the architecture and circuit design of Flash Memories (3D NAND/NOR), SRAM, Emerging Memories (FeRAM,PCM) and CiM(Compute-in-Memory).

Experience

Stealth ModeCreator

2025 — Now

Sunnyvale, California, United States

Design the super low power and high speed circuit.

ANAFLASH IncDesign Team Lead

2021 — 2024

San Jose, California, United States

Standard Logic Compatible Embedded Flash Memory IP development

Battery Powered AI Acceleration Solution by using Analog Compute-in-Memory with Logic-EFLASH

Yangtze Memory TechnologiesTechnical Director

2016 — 2021

San Jose, CA

3D NAND Flash Design

Chip Architecturing/Floor planning and power/signal line planning

Core area circuit design

Fullchip simulation/Power network analysis/IR drop and EM simulation

QualcommSenior Staff Engineer

2012 — 2016

Designed various SRAM product(SP, Multi-port, RF, PDP) and OTP memory by using 28nm SOC and 16nm/14nm/10nm/7nm Finfet technology.

Contour SemiconductorDirector Of Design

2007 — 2012

Billerica, MA

Design of Storage Class Memory (1G NAND compatible spec) product using PCM (phase change memory) technology with NMOS only transistor.

Experience+3

Experience